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기능 64M20C Client Compute NAND Flash Memory
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29F16B08MCMFS 데이터시트, 핀배열, 회로
Intel® 64M20C Client Compute NAND Flash
Memory
PF29F64G08LCMFS, PF29F16B08MCMFS, PF29F32B08NCMFS
Advance Datasheet
Product Features
Open NAND Flash Interface (ONFI) 3.0-compliant Command set: ONFI NAND Flash Protocol
Multi-level cell (MLC) technology
Advanced command set:
Organization
— Page size: 17,600 bytes (16,384 + 1216)
— Block size: 512 pages, (8,192K + 608K
bytes)
— Plane size: 2 planes x 512 blocks
Device size:
— 64 Gb: 1,024 blocks
— 128Gb: 2,048 blocks
— 256Gb: 4,096 blocks
Synchronous I/O performance
— Up to timing mode 6
— Clock rate: 6ns
— Read/write throughput per pin: 333 MT/s
Asynchronous I/O performance
— Up to asynchronous timing mode 5
tRC/tWC: 20ns (MIN)
— Read/write throughput per pin: 50 MT/s
Array performance
— Read page: 65us (TYP), 110us (MAX)
— Program page: 1,250us (TYP)
— Erase block: 5ms (TYP)
— PAGE CACHE PROGRAM
— READ CACHE
(RANDOM, SEQUENTIAL, END)
— READ UNIQUE ID
— COPYBACK
— Multi-LUN operations
— Multi-plane commands
— Read unique ID
Copyback operations supported within the
plane that the data was read
First block (block address 00h) is valid when
shipped from factory.
RESET (FFh) required as first command after
power-on
Operation status byte provides software
method for detecting
— Operation completion
— Pass/fail condition
— Write-protect status
Data strobe (DQS) signals provide a hardware
method for synchronizing data DQ in the
synchronous interface
Operating Voltage Range
On-die Termination (ODT)
— VCC: 2.7–3.6V
Operating temperature: 0°C to +70°C
— VCCQ: 1.7–1.95V or 2.7–3.6V (Async only) Package: 132-ball BGA
Density
64Gb
128Gb
256Gb
Package
BGA
BGA
BGA
# of Die
SDP
DDP
QDP
1
2
4
# of CE#
and R/B#
1
2
4
Bus I/O
Configuration
Single x8
Dual x8
Dual x8
Device ID
89h, 64h, 64h, 3Ch, A1h, 00h, 00h, 00h
89h, 64h, 64h, 3Ch, A1h, 00h, 00h, 00h
89h, 64h, 64h, 3Ch, A1h, 00h, 00h, 00h
Intel Confidential
Document Number: 328959-001US
May 2013




29F16B08MCMFS pdf, 반도체, 판매, 대치품
Intel® 64M20C Client Compute NAND Flash Memory
9.1 Activating the Asynchronous Interface ..................................................................56
9.2 Activating the Synchronous ONFI 2.3 Interface ......................................................56
9.3 Activating the Synchronous ONFI 3.0 Interface ......................................................57
10.0 CE# Pin Reduction and Volume Addressing ..............................................................58
10.1 Initialization Sequence .......................................................................................60
10.2 Volume Appointment without CE# Pin Reduction ....................................................61
10.3 Appointing Volume Addresses..............................................................................62
10.4 Selecting a Volume ............................................................................................62
10.5 Multiple Volume Operation Restrictions .................................................................62
10.6 Volume Reversion ..............................................................................................63
11.0 Command Definitions ...............................................................................................64
12.0 Reset Operations .....................................................................................................66
12.1 RESET (FFh) .....................................................................................................66
12.2 SYNCHRONOUS RESET (FCh) ..............................................................................67
12.3 RESET LUN (FAh)...............................................................................................67
13.0 Identification Operations .........................................................................................69
13.1 READ ID (90h) ..................................................................................................69
13.2 READ ID Parameter Tables..................................................................................70
13.3 READ PARAMETER PAGE (ECh) ............................................................................72
13.4 READ UNIQUE ID (EDh)......................................................................................73
14.0 Configuration Operations .........................................................................................74
14.1 SET FEATURES (EFh)..........................................................................................75
14.2 GET FEATURES (EEh) .........................................................................................75
14.3 VOLUME SELECT (E1h) .......................................................................................79
14.4 ODT CONFIGURE (E2h) ......................................................................................81
15.0 Status Operations ....................................................................................................83
15.1 READ STATUS (70h) ..........................................................................................84
15.2 READ STATUS ENHANCED (78h) ..........................................................................85
16.0 Column Address Operations .....................................................................................86
16.1 CHANGE READ COLUMN (05h-E0h) ......................................................................86
16.2 CHANGE READ COLUMN ENHANCED (06h-E0h)......................................................87
16.3 CHANGE READ COLUMN ENHANCED (00h-05h-E0h) Operation.................................88
16.4 CHANGE WRITE COLUMN (85h) ...........................................................................88
16.5 CHANGE ROW ADDRESS (85h) ............................................................................89
17.0 Read Operations ......................................................................................................90
17.1 Read Operations ................................................................................................90
17.2 Read Cache Operations.......................................................................................90
17.3 Multi-Plane Read Operations................................................................................91
17.4 READ MODE (00h) .............................................................................................92
17.5 READ PAGE (00h-30h)........................................................................................92
17.6 READ PAGE CACHE SEQUENTIAL (31h).................................................................93
17.7 READ PAGE CACHE RANDOM (00h-31h)................................................................94
17.8 READ PAGE CACHE LAST (3Fh) ............................................................................95
17.9 READ PAGE MULTI-PLANE (00h-32h) ....................................................................96
18.0 Program Operations.................................................................................................98
18.1 PROGRAM PAGE (80h-10h) .................................................................................99
18.2 PROGRAM PAGE CACHE (80h-15h)..................................................................... 100
18.3 PROGRAM PAGE MULTI-PLANE (80h-11h) ........................................................... 102
19.0 Erase Operations.................................................................................................... 104
Intel® 64M20C Client Compute NAND Flash Memory
Advance Datasheet
4 Intel Confidential
May 2013
Document Number: 328959-001US

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29F16B08MCMFS 전자부품, 판매, 대치품
Intel® 64M20C Client Compute NAND Flash Memory
1.0
1.1
Overview
NAND flash technology provides a cost-effective solution for applications requiring
high-density solid-state storage. The Intel® 64M20C device is available in three
densities:
• 64 Gb
• 128 Gb
• 256 Gb
Intel® NAND Flash Memory devices include standard NAND flash features and new
features designed to enhance system-level performance. For a summary of
performance and reliability specifications, see “Product Features” on page 1. Details are
available in subsequent sections in this document.
These NAND devices are ONFI 3.0-compliant and support an asynchronous interface
only. The ONFI 3.0 specification can be found at www.onfi.org.
Architecture
Intel NAND Flash Memory devices offer an asynchronous data interface for high-
performance I/O operations. These devices use a highly multiplexed 8-bit bus (DQx) to
transfer commands, addresses, and data.
Five control signals implement the asynchronous interface: CE#, CLE, ALE, WE# and
RE#. Additional signals control hardware write protection (WP#) and monitor device
status (R/B#).
Some versions of this Intel NAND Flash device additionally include a synchronous data
interface for high-performance I/O operations. When the synchronous interface is
active, WE# becomes CLK and RE# becomes W/R#. Data transfers include a
bidirectional data strobe (DQS).
This hardware interface creates a low-pin-count device with a standard pinout that
remains the same from one density to another, enabling future upgrades to higher
densities with no board redesign.
A target is the unit of memory accessed by a chip enable signal. A target contains one
or more NAND flash die. A NAND flash die is the minimum unit that can indepentently
execute commands and report status. A NAND flash die in the ONFI specification is
referred to as a logical unit (LUN). There is one LUN per CE#.
The contents of each page can be programmed in tPROG, and an entire block can be
erased in tBERS.
May 2013
Document Number: 328959-001US
Intel Confidential
Intel® 64M20C Client Compute NAND Flash Memory
Advance Datasheet
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64M20C Client Compute NAND Flash Memory

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