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AR2316 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 AR2316
기능 Single Chip MAC/Baseband/Radio and Processor
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AR2316 데이터시트, 핀배열, 회로
Data Sheet
PRELIMINARY
May 2005
AR2316 Single Chip MAC/Baseband/Radio and Processor
for 2.4 GHz Wireless LANs
General Description
The Atheros AR2316 integrated the MAC/
baseband/radio and processor into a single
chip for wireless access point and router
applications. It includes a 2.4 GHz radio, MIPS
4000 processor, 802.11 MAC/baseband
processor, 802.3 Ethernet MAC and MII
interface, SDRAM controller, external memory
interface for Flash, ROM, or RAM, PCI bus
interface or a flexible local bus, UART, GPIOs,
LED controls.
The AR2316 implements an 802.11 MAC/
baseband processor supporting all IEEE
802.11g data rates (1 to 54 Mbps) and all IEEE
802.11b complementary key coding (CCK) data
rates (1 to 11 Mbps). In Atheros Super G
mode, AR2316 supports data rates up to 108
Mbps. Additional features include forward
error correction coding at rates for
1/2, 2/3, and 3/4, signal detection, automatic
gain control, frequency offset estimation,
symbol timing, channel estimation, error
recovery, enhanced security, and quality of
service (QoS). The AR2316 performs receive
and transmit filtering for IEEE 802.3 and 802.11
networks.
The AR2316 is an all CMOS, highly integrated
single-chip solution that supports 802.11b/g
WLANs.
Features
Integrated MIPS 4000 processor
180 MHz processor frequency
IEEE 802.11b/g Access Point, Ad Hoc, and
station functions supported
OFDM and CCK modulation schemes
supported
Data rates of 1, 2, 5.5, 6, 9, 11, 12, 18, 24, 36,
48, 54 Mbps and Atheros Super Gmode
offering up to 108 Mbps
IEEE 802.3 Ethernet MAC supporting 10/
100 Mbps, full and half duplex, and MII
interface to external Ethernet PHY
UART for console support
Flexible, programmable local bus
PCI bus host and client modes
IEEE 1149.1 standard test access port and
boundary scan architecture supported
EJTAG based debugging of the processor
core supported
Standard 0.18 µm CMOS technology
15 mm x 15 mm 233 PBGA package
System Block Diagram
RF RF
Filter Switch
Receiver
Frequency
Synthesizer
Transmitter
Bias/Control
Controls
SDRAM
Controller
and Memory
Interface
ADC
MIPS
Processor
DAC
AR2316
Baseband(PHY)
and Wireless
MAC
Ethernet MAC
Fast UART
Local Bus
Peripheral
Interface
Flash
SDRAM Interface
MII Interface
40 MHz
Crystal
Serial Interface
Parallel Interface
LED Controls
GPIOs
© 2000-2005 by Atheros Communications, Inc. All rights reserved. Atheros™, 5-UP™, Driving the Wireless Future™, Atheros Driven™, Atheros Turbo
Mode™, and the Air is Cleaner at 5-GHz™ are trademarks of Atheros Communications, Inc. The Atheros logo is a registered trademark of
Atheros Communications, Inc. All other trademarks are the property of their respective holders.
Subject to change without notice.
COMPANY CONFIDENTIAL
1




AR2316 pdf, 반도체, 판매, 대치품
3.1.36 Scratch Register 1
(RST_SCRATCH1) 39
3.1.37 Observation Control
(RST_OBS_CTL) 39
3.1.38 General Clock Control
(RST_MISCCLK_CTL) 40
3.1.39 Client Interrupt Mask
(RST_CIMR) 41
3.1.40 PLL Programming Notes 41
3.2 SDR-DRAM Controller Registers 42
3.2.1 SDR-DRAM Configuration Reg-
ister (MEMCTL_SCONR) 42
3.2.2 SSDR-DRAM Timing Register 0
(MEMCTL_STMG0R) 43
3.2.3 SDR-DRAM Timing Register 1
(MEMCTL_STMG1R) 44
3.2.4 SDR-DRAM Control Register
(MEMCTL_SCTLR) 45
3.2.5 SDR-DRAM Refresh Interval
Register (MEMCTL_SREFR) 45
3.3 UART Registers 46
3.3.1 Receive Buffer Register
(UART_RBR); Transmit Holding
Register (UART_THR); Divisor
Latch Low Register
(UART_DLL) 46
3.3.2 Interrupt Enable Register
(UART_IER); Divisor Latch High
(UART_DLH) 46
3.3.3 Interrupt Identity Register
(UART_IIR); FIFO Control Regis-
ter (UART_FCR) 47
3.3.4 Line Control Register
(UART_LCR) 47
3.3.5 Modem Control Register
(UART_MCR) 48
3.3.6 Line Status Register
(UART_LSR) 48
3.3.7 Modem Status Register
(UART_MSR) 49
3.3.8 Scratch Register
(UART_SCR) 49
3.4 Local Bus Interface Registers 50
3.4.1 Protocol Configuration Register
(LB_PCFG) 50
3.4.2 One Millisecond Prescaler
(LB_1MS) 52
3.4.3 Miscellaneous Configuration
(LB_MCFG) 52
3.4.4 Rx Timestamp Offset
(LB_RxTSOFF) 53
3.4.5 Host Configuration
(LB_HOST) 53
3.4.6 Tx Chain Enable (LB_FTxE) 54
3.4.7 Tx Chain Disable (LB_FTxD) 54
3.4.8 Tx Descriptor Pointer
(LB_FTxDP) 54
3.4.9 Rx Chain Enable (LB_FRxE) 55
3.4.10 Rx Chain Disable
(LB_FRxD) 55
3.4.11 Rx Descriptor Pointer
(LB_FRxDP) 55
3.4.12 Interrupt Status (LB_ISR) 56
3.4.13 Interrupt Mask (LB_IMR) 57
3.4.14 Interrupt Enable (LB_IER) 57
3.4.15 AR2316-to-Host Mailbox
(LB_MBOX_F2H) 57
3.4.16 Host-to-AR2316 Mailbox
(LB_MBOX_H2F) 58
3.4.17 PIO Access Range (LB_PIO) 58
3.5 PCI Interface Registers 58
3.5.1 One Millisecond Prescaler
(PCI_1MS) 59
3.5.2 Miscellaneous Configuration
(PCI_MCFG) 59
3.5.3 Rx Timestamp Offset
(PCI_RxTSOFF) 60
3.5.4 PCI Non-Cachable Segment
Configuration
(PCI_NCCFG) 61
3.5.5 Tx Chain Enable (PCI_FTxE) 61
3.5.6 Tx Chain Disable
(PCI_FTxD) 62
3.5.7 Tx Descriptor Pointer
(PCI_FTxDP) 62
3.5.8 Rx Chain Enable
(PCI_FRxE) 62
3.5.9 Rx Chain Disable
(PCI_FRxD) 62
3.5.10 Rx Descriptor Pointer
(PCI_FRxDP) 63
3.5.11 Interrupt Status (PCI_ISR) 63
3.5.12 Interrupt Mask (PCI_IMR) 64
3.5.13 Interrupt Enable (PCI_IER) 65
3.5.14 Host Interrupt Mask
4 • AR2316 MAC/BB/Radio and Processor for 2.4 GHz WLANs
Atheros Communications, Inc.
COMPANY CONFIDENTIAL

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AR2316 전자부품, 판매, 대치품
PRELIMINARY
1. Pin Descriptions
This section contains both a package pinout
(see Table 1-1 through Table 1-5) and tabular
listings of the signal descriptions.
The following nomenclature is used for signal
names:
NC indicates no connection should be made
to this pin.
_L at the end of the signal name indicates
active low signal.
P at the end of the signal name indicates the
positive side of a differential signal.
N at the end of the signal name indicates the
negative side of a differential signal.
The following nomenclature is used for signal
types:
IA indicates an analog input signal.
I indicates a digital input signal.
IH indicates input signals with weak
internal pull-up, to prevent signals from
floating when left open.
IL indicates input signals with weak
internal pull-down, to prevent signals from
floating when left open.
I/O indicates a digital bidirectional signal.
OA indicates an analog output signal.
O indicates a digital output signal.
P indicates a power or ground signal.
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
AR2316 MAC/BB/Radio and Processor for 2.4 GHz WLANs • 7
May 2005 7

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