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STD25P03L 데이터시트 PDF




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기능 Power MOSFET ( Transistor )
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STD25P03L 데이터시트, 핀배열, 회로
NTD25P03L, STD25P03L
Power MOSFET
−25 A, −30 V, Logic Level P−Channel DPAK
Designed for low voltage, high speed switching applications and to
withstand high energy in the avalanche and commutation modes.
The source−to−drain diode recovery time is comparable to a discrete
fast recovery diode.
Features
S Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements; AEC−Q101 Qualified and
PPAP Capable
These Devices are Pb−Free and are RoHS Compliant
Typical Applications
PWM Motor Controls
Power Supplies
Converters
Bridge Circuits
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Symbol Value
Unit
Drain−to−Source Voltage
Gate−to−Source Voltage
− Continuous
− Non−Repetitive (tp 10 ms)
Drain Current
− Continuous @ TA = 25°C
− Single Pulse (tp 10 ms)
Total Power Dissipation @ TA = 25°C
Operating and Storage Temperature Range
VDSS
VGS
VGSM
ID
IDM
PD
TJ, Tstg
−30
±15
±20
−25
−75
75
−55 to
+150
V
V
Vpk
A
Apk
W
°C
Single Pulse Drain−to−Source Avalanche
EAS 200 mJ
Energy − Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 5.0 Vdc,
Peak IL = 20 Apk, L = 1.0 mH, RG = 25 W)
Thermal Resistance
− Junction−to−Case
− Junction−to−Ambient (Note 1)
− Junction−to−Ambient (Note 2)
RqJC
RqJA
RqJA
°C/W
1.65
67
120
Maximum Lead Temperature for Soldering
Purposes, (1/8 in from case for 10 seconds)
TL
260 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. When surface mounted to an FR4 board using 0.5 sq in pad size.
2. When surface mounted to an FR4 board using the minimum recommended
pad size.
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V(BR)DSS
−30 V
RDS(on) Typ
51 mW @ 5.0 V
D
ID Max
−25 A
P−Channel
G
S
4
12
3
DPAK
CASE 369C
STYLE 2
MARKING DIAGRAM
& PIN ASSIGNMENT
4
Drain
1
Gate
2
Drain
3
Source
A
Y
WW
25P03L
G
= Assembly Location*
= Year
= Work Week
= Device Code
= Pb−Free Package
* The Assembly Location code (A) is front side
optional. In cases where the Assembly Location is
stamped in the package, the front side assembly
code may be blank.
ORDERING INFORMATION
See detailed ordering and shipping information on page 7 of
this data sheet.
© Semiconductor Components Industries, LLC, 2014
September, 2014 − Rev. 5
1
Publication Order Number:
NTD25P03L/D




STD25P03L pdf, 반도체, 판매, 대치품
NTD25P03L, STD25P03L
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Dt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (IG(AV)) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, VSGP. Therefore, rise and fall
times may be approximated by the following:
tr = Q2 x RG/(VGG − VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG − VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off−state condition when
calculating td(on) and is read at a voltage corresponding to the
on−state when calculating td(off).
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
2200
2000 Ciss
1800
TJ = 25°C
1600
1400
1200 Crss
1000
Ciss
800
600
400
200
0
10
Coss
VDS = 0 V VGS = 0 V
Crss
5 0 5 10 15 20
−VGS
−VDS
GATE−TO−SOURCE OR DRAIN−TO−SOURCE
VOLTAGE (VOLTS)
25
Figure 7. Capacitance Variation
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STD25P03L 전자부품, 판매, 대치품
NTD25P03L, STD25P03L
TYPICAL ELECTRICAL CHARACTERISTICS
1
D = 0.5
0.2
0.1
0.1 0.05
0.02
0.01
SINGLE PULSE
0.01
1.0E−05
1.0E−04
P(pk)
t1
t2
DUTY CYCLE, D = t1/t2
RqJC(t) = r(t) RqJC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) − TC = P(pk) RqJC(t)
1.0E−03
1.0E−02
1.0E−01
t, TIME (s)
Figure 13. Thermal Response
1.0E+00
1.0E+01
IS
tp
di/dt
trr
ta tb
0.25 IS
IS
TIME
Figure 14. Diode Reverse Recovery Waveform
ORDERING INFORMATION
Device
NTD25P03LT4G
Package
DPAK
(Pb−Free)
Shipping
2500 / Tape & Reel
STD25P03LT4G*
DPAK
(Pb−Free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*S Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP
Capable.
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STD25P03L

Power MOSFET ( Transistor )

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