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71M6545 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 71M6545
기능 Metrology Processors
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71M6545 데이터시트, 핀배열, 회로
71M6545/71M6545H
Metrology Processors
GENERAL DESCRIPTION
The 71M6545/71M6545H metrology processors are based on
4th-generation metering architecture supporting the 71M6xxx
series of isolated current sensing products that offer drastic
reduction in component count, immunity to magnetic tampering,
and unparalleled reliability. The 71M6545/71M6545H integrate
our Single Converter Technology® with a 22-bit delta-sigma
ADC, a customizable 32-bit computation engine (CE) for core
metrology functions, as well as a user-programmable 8051-
compatible application processor (MPU) core with up to 64KB
flash and up to 5KB RAM.
An external host processor can access metrology functions di-
rectly through the SPI™ interface, or alternatively through the
embedded MPU core in applications requiring metrology data
capture, storage, and preprocessing within the metrology
subsystem. In addition, the devices integrate an RTC, DIO, and
UART. A complete array of ICE and development tools,
programming libraries, and reference designs enable rapid
development and certification of meters that meet all ANSI and
IEC electricity metering standards worldwide.
C Shunt Resistor Sensors
NEUTRAL
B
A
LOAD
HOST
POWER SUPPLY
This system is referenced to Neutral
NEUTRAL
Pulse Transformers
C
B
A
SPI_CKI
SPI_DI
SPI_DO
SPI_CSZ
XFER_BUSY
SAG
MUX and ADC
IADC0
IADC1
} IN*
VADC10 (VC)
IADC6
IADC7
}
IC
VADC9 (VB)
IADC4
IADC5
}
IB
VADC8(VA)
IADC2
IADC3
} IA
V3P3A V3P3SYS GNDA GNDD
PWR MODE
CONTROL
71M6545/H
PB
REGULATOR
TEMPERATURE
SENSOR
VBAT_RTC
BATTERY
MONITOR
VREF
SERIAL PORT
RX
TX
FLASH
MEMORY
RAM
MPU
RTC
TIMERS
OSCILLATOR/
PLL XIN
XOUT
DIO, PULSES,
LEDs
DIO
ICE
T
SPI INTERFACE
M
U
COMPUTE
ENGINE
X
V3P3D
WPULSE
XPULSE
RPULSE
YPULSE
10/7/2010
RTC
BATTERY
32 kHz
24
DIO
I2C or µWire
EEPROM
PULSES 3.3 VDC
*IN = Optional Neutral Current
FEATURES
0.1% Typical Accuracy Over 2000:1
Current Range
Exceeds IEC 62053/ANSI C12.20 Standards
Seven Sensor Inputs with Neutral Current
Measurement, Differential Mode Selectable
for Current Inputs
Selectable Gain of 1 or 8 for One Current
Input to Support Shunts
High-Speed Wh/VARh Pulse Outputs with
Programmable Width
Flash/RAM Size
32KB/3KB (71M6545)
64KB/5KB (71M6545H)
Up to Four Pulse Outputs with Pulse Count
Four-Quadrant Metering, Phase
Sequencing
Digital Temperature Compensation
Metrology Compensation
Accurate RTC for TOU Functions with
Automatic Temperature Compensation
for Crystal in All Power Modes
Independent 32-Bit Compute Engine
46–64Hz Line Frequency Range with the
Same Calibration
Phase Compensation (±7°)
1µA Supply Current in Sleep Mode
Flash Security
In-System Program Update
8-Bit MPU (80515), Up to 5 MIPS, for
Optional Implementation of Postprocessing
and Host Support Functions (Optional Use)
Up to 29 DIO Pins
Hardware Watchdog Timer (WDT)
I2C/MICROWIRE® EEPROM Interface
SPI Interface for Host:
Full Access to Shared Memory Space
Flash Program Capability
UART
Industrial Temperature Range
64-Pin Lead(Pb)-Free LQFP Package
Single Converter Technology is a registered trademark of Maxim Integrated Products, Inc.
MICROWIRE is a registered trademark of National Semiconductor Corp.
For pricing, delivery, and ordering information, please contact Maxim Direct at
19-5378; Rev 2; 10/13
1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.




71M6545 pdf, 반도체, 판매, 대치품
71M6545/71M6545H Data Sheet
PDS_6545_009
6 71M6545/H Specifications .............................................................................................................. 113
6.1 Absolute Maximum Ratings ..................................................................................................... 113
6.2 Recommended External Components..................................................................................... 114
6.3 Recommended Operating Conditions...................................................................................... 114
6.4 Performance Specifications ..................................................................................................... 115
6.4.1 Input Logic Levels........................................................................................................ 115
6.4.2 Output Logic Levels ..................................................................................................... 115
6.4.3 Battery Monitor............................................................................................................. 115
6.4.4 Temperature Monitor ................................................................................................... 116
6.4.5 Supply Current ............................................................................................................. 117
6.4.6 V3P3D Switch .............................................................................................................. 117
6.4.7 Internal Power Fault Comparators............................................................................... 118
6.4.8 2.5 V Voltage Regulator – System Power ................................................................... 118
6.4.9 Crystal Oscillator.......................................................................................................... 118
6.4.10 Phase-Locked Loop (PLL) ........................................................................................... 119
6.4.11 71M6545/H VREF........................................................................................................ 120
6.4.12 ADC Converter (71M6545/H) ...................................................................................... 121
6.4.13 Pre-Amplifier for IADC0-IADC1 ................................................................................... 122
6.5 Timing Specifications ............................................................................................................... 123
6.5.1 Flash Memory .............................................................................................................. 123
6.5.2 SPI Slave ..................................................................................................................... 123
6.5.3 EEPROM Interface ...................................................................................................... 123
6.5.4 RESET Pin................................................................................................................... 124
6.5.5 Real-Time Clock (RTC) ............................................................................................... 124
6.6 64-Pin LQFP Package Outline Drawing .................................................................................. 125
6.7 71M6545/H Pinout ................................................................................................................... 126
6.8 71M6545/H Pin Descriptions ................................................................................................... 127
6.8.1 71M6545/H Power and Ground Pins........................................................................... 127
6.8.2 71M6545/H Analog Pins .............................................................................................. 128
6.8.3 71M6545/H Digital Pins ............................................................................................... 129
6.8.4 I/O Equivalent Circuits ................................................................................................. 130
7 Ordering Information ...................................................................................................................... 131
7.1 71M6545/H Ordering Guide..................................................................................................... 131
8 Related Information...................................................................................................................... 131
9 Contact Information ..................................................................................................................... 131
Appendix A: Acronyms .......................................................................................................................... 132
Appendix B: Revision History ............................................................................................................... 133
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71M6545 전자부품, 판매, 대치품
71M6545/71M6545H Data Sheet
Table 50: SPI Transaction Fields................................................................................................................ 61
Table 51: SPI Command Sequences.......................................................................................................... 62
Table 52: SPI Registers .............................................................................................................................. 62
Table 53: TMUX[4:0] Selections ................................................................................................................. 64
Table 54: TMUX2[4:0] Selections ............................................................................................................... 65
Table 55: Available Circuit Functions.......................................................................................................... 67
Table 56: VSTAT[2:0] (SFR 0xF9[2:0])........................................................................................................ 68
Table 57: GAIN_ADJn Compensation Channels (Figure 2, Figure 27, Table 1)........................................ 76
Table 58: GAIN_ADJx Compensation Channels (Figure 3, Figure 28, Table 2) ........................................ 78
Table 59: I/O RAM Map – Functional Order, Basic Configuration .............................................................. 82
Table 60: I/O RAM Map – Functional Order ............................................................................................... 84
Table 61: I/O RAM Map – Alphabetical Order ............................................................................................ 88
Table 62. Info Page Trim Fuses.................................................................................................................. 98
Table 63: CE EQU[2:0] Equations and Element Input Mapping............................................................... 101
Table 64: CE Raw Data Access Locations ............................................................................................... 102
Table 65: CESTATUS Register................................................................................................................... 103
Table 66: CESTATUS Bit Definitions .......................................................................................................... 103
Table 67: CECONFIG Register.................................................................................................................. 103
Table 68: CECONFIG Bit Definitions (CE RAM 0x20)............................................................................... 104
Table 69: Sag Threshold, Phase Measurement, and Gain Adjust Control............................................... 105
Table 70: CE Transfer Variables (with Shunts)......................................................................................... 105
Table 71: CE Transfer Variables (with CTs) ............................................................................................. 106
Table 72: CE Energy Measurement Variables (with Shunts) ................................................................... 106
Table 73: CE Energy Measurement Variables (with CTs) ........................................................................ 106
Table 74: Other Transfer Variables........................................................................................................... 107
Table 75: CE Pulse Generation Parameters............................................................................................. 108
Table 76: CE Parameters for Noise Suppression and Code Version ....................................................... 109
Table 77: CE Calibration Parameters ....................................................................................................... 110
Table 78: Absolute Maximum Ratings ...................................................................................................... 113
Table 79: Recommended External Components ...................................................................................... 114
Table 80: Recommended Operating Conditions....................................................................................... 114
Table 81: Input Logic Levels ..................................................................................................................... 115
Table 82: Output Logic Levels .................................................................................................................. 115
Table 83: Battery Monitor Performance Specifications (TEMP_BAT = 1) ................................................. 115
Table 84. Temperature Monitor ................................................................................................................ 116
Table 85: Supply Current Performance Specifications ............................................................................. 117
Table 86: V3P3D Switch Performance Specifications .............................................................................. 117
Table 87: 2.5 V Voltage Regulator Performance Specifications (VDD pin).............................................. 118
Table 88: Crystal Oscillator Performance Specifications.......................................................................... 118
Table 89: PLL Performance Specifications............................................................................................... 119
Table 90: 71M6545/H VREF Performance Specifications........................................................................ 120
Table 91: ADC Converter Performance Specifications............................................................................. 121
Table 92: Pre-Amplifier Performance Specifications ................................................................................ 122
Table 93: Flash Memory Timing Specifications ........................................................................................ 123
Table 94. SPI Slave Timing Specifications ............................................................................................... 123
Table 95: EEPROM Interface Timing........................................................................................................ 123
Table 96: RESET Pin Timing .................................................................................................................... 124
Table 97: RTC Range for Date ................................................................................................................. 124
Table 98: 71M6545/H Power and Ground Pins ........................................................................................ 127
Table 99: 71M6545/H Analog Pins ........................................................................................................... 128
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