NB3L83948C Datasheet PDF - ON Semiconductor
| Part Number | NB3L83948C | |
| Description | 2.5V / 3.3V Differential and LVTTL/LVCMOS 2:1 MUX to 1:12 LVCMOS Fanout | |
| Manufacturers | ON Semiconductor | |
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NB3L83948C
2.5 V / 3.3 V Differential and
LVTTL/LVCMOS 2:1 MUX to
1:12 LVCMOS Fanout
Description
The NB3L83948C is a pure 2.5 V / 3.3 V (VDD = VDDO) or mixed
mode 3.3 V Core (VDD) / 2.5 V Output (VDDO) clock distribution
buffer with the capability to select either a differential LVPECL /
LVDS / LVHSTL / SSTL / HCSL or single ended LVCMOS / LVTTL
compatible input clock, such as a Primary or a Test Clock. All other
control inputs (CLK_SEL, CLK_EN, and OE) are LVTTL/LVCMOS
level compatible.
The NB3L83948C provides an enable input, CLK_EN pin, which
synchronously enables or disables the clock outputs while in the LOW
state. Since this input is internally synchronized to the input clock,
changing only when the input is LOW, potential output glitching or
runt pulse generation is eliminated.
The 12 LVCMOS output pins drive 50 W series or parallel
terminated transmission lines. The outputs can also be disabled to a
high impedance (tri−stated) via the OE input, or enabled when High.
Fit, Form, and Function compatible with ICS83948I−147,
ICS83948I−01, CY29948AXI, and MPC9448/9448L
Features
• 2.5 V / 3.3V (VDD = VDDO) or
3.3 V VDD / 2.5 V VDDO Operation:
2.5 $5%, 2.375 to 2.625 V
3.3 $5%; 3.135 to 3.465 V
• 350 MHz Clock Support
• Accepts LVPECL, LVDS, LVHSTL, SSTL, HCSL, or LVCMOS
Clock Inputs
• LVCMOS Compatible Control Inputs
• 12 LVCMOS Clock Outputs
• Synchronous Clock Select
• Output Enable to High Z State Control
• 100 ps Max. Skew Between Outputs
• Industrial Temp. Range −40°C to +85°C
• 32−pin LQFP Package
• These are Pb−Free Devices
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MARKING
DIAGRAMS*
LQFP−32
FA SUFFIX
CASE 873A
NB3L
83948C
AWLYYWWG
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
(*Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
VDDO
VDD
GND
Q0
Q1
CLK_EN
LVCMOS_CLK
CLK
CLK
CLK_SEL
D
Q
1
2
Q2
Q3
Q4
Q5
Q6
VDDO
Q7
Q8
Q9
Q10
Q11
OE
Figure 1. Simplified Logic Diagram
ORDERING INFORMATION
See detailed ordering and shipping information on page 6 of
this data sheet.
© Semiconductor Components Industries, LLC, 2014
November, 2014 − Rev. 2
1
Publication Order Number:
NB3L83948C/D
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NB3L83948C
Table 6. AC CHARACTERISTICS VDD = VDDO = 3.3 $5% (3.135 to 3.465 V) or 2.5 $5% (2.375 to 2.625 V); VDD = 3.3 $5%
(3.135 to 3.465 V) and VDDO = 2.5 $5% (2.375 to 2.625 V) GND = 0 V, TA = −40°C to +85°C; (Note 5)
Symbol
Characteristic
Min Typ Max Unit
Fmax
tPLH/tPHL
tPZL/tPZH
tPLZ/tPHZ
tSKEWDC
tSKEWD−D
Maximum Operating Frequency
Propagation Delay, (crosspoint to VDDO/2) f ≤ 350 MHz
3.3 V VDD = VDDO or 3.3 V VDD, 2.5 V VDDO; CLK/CLK to Qx
3.3 V VDD = VDDO or 3.3 V VDD, 2.5 V VDDO; 3.3 V LVCMOS_CLK to Qx
2.5 V VDD = VDDO CLK/CLK to Qx
2.5 V VDD = VDDO LVCMOS_CLK to Qx
Output Enable Time OE to Qx
Output Disable Time OE to Qx
Duty Cycle Skew at VDD / 2
At 150 MHz; 3.3 V VDD = VDDO
At 200 MHz; 2.5 V VDD = VDDO
At 150 MHz; 2.5 V VDD = VDDO
Device to Device Skew (similar condition)
CLK/CLK to Qx; CLK to Qx
350
1.6
1.0
1.6
1.0
45
45
40
MHz
ns
3.6 ns
3.0
3.6
3.0
5 ns
5 ns
%
55
55
60
ns
1.0
tSKEWO−O
tS
Output to Output Skew Within A Device
Set−up Time to CLK tf
CLK_EN to CLK/CLK
CLK_EN to CLK
1.0
0.0
25 100 ps
ns
tH Hold Time to CLK tf
CLK/CLK to CLK_EN
CLK to CLK_EN
0.0
1.0
ns
tr/tf Output rise and fall times
(0.8 V and 2.0 V) 3.3 V VDD = VDDO
(0.6 V and 1.8 V) or 3.3 V VDD, 2.5 VDDO
(0.6 V and 1.8 V) 2.5 V VDD = VDDO
ns
1.0
1.0
1.3
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Outputs loaded with 50 W to VTT (VDDO/2); see Figure 5. CLOCK input with 50% duty cycle. Measured at CLK/CLK crosspoint to Qx VDDO/2,
CLK VDDO/2 to Qx VDDO/2; see Figure 4.
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