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NB3F8L3010C 데이터시트 PDF




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부품번호 NB3F8L3010C 기능
기능 3.3V / 2.5V / 1.8V / 1.5V 3:1:10 LVCMOS Fanout Buffer
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NB3F8L3010C 데이터시트, 핀배열, 회로
NB3F8L3010C
3.3V / 2.5V / 1.8V / 1.5V
3:1:10 LVCMOS Fanout Buffer
Description
The NB3F8L3010C is a 3:1:10 Clock / Data fanout buffer operating
on a 3.3 V / 2.5 V Core VDD and two flexible 3.3 V / 2.5 V / 1.8 V /
1.5 V VDDOn supplies which must be equal or less than VDD.
A Mux selects between a Crystal input, or either of two
differential/SE Clock / Data inputs. Differential Inputs accept
LVPECL, LVDS, HCSL, or SSTL and Single−Ended levels. The
MUX control lines, SEL0 and SEL1, select CLK0/CLK0,
CLK1/CLK1, or Crystal input pins per Table 3. The Crystal input is
disabled when a Clock input is selected. Output enable pin, OE,
synchronously forces a High Impedance state (HZ) when Low per
Table 4.
Outputs consist of 10 single−ended LVCMOS outputs.
Features
Ten CMOS / LVTTL Outputs up to 200 MHz
Differential Inputs Accept LVPECL, LVDS, HCSL, or SSTL
Crystal Oscillator Interface
Crystal Input Frequency Range: 10 MHz to 50 MHz
Output Skew: 10 ps Typical
Additive RMS Phase Jitter @ 125 MHz, (12 kHz – 20 MHz): 0.03 ps
(Typical)
Synchronous Output Enable
Output Defined Level When Input is Floating
Power Supply Modes:
Single 3.3 V
Single 2.5 V
Mixed 3.3 V ± 5% Core/2.5 V ± 5% Output Operating Supply
Mixed 3.3 V ± 5% Core/1.8 V ± 0.2 V Output Operating Supply
Mixed 3.3 V ± 5% Core/1.5 V ± 0.15 V Output Operating Supply
Mixed 2.5 V ± 5% Core/ 1.8 V ± 0.2 V Output Operating Supply
Mixed 2.5 V ± 5% Core /1.5 V ± 0.15 V Output Operating Supply
Two Separate Output Bank Power Supplies
Industrial temp. range -40°C to 85°C
These are Pb−Free Devices
Applications
Clock Distribution
Networking and Communications
High End Computing
Wireless and Wired Infrastructure
End Products
Servers
Ethernet Switch/Routers
ATE
Test and Measurement
www.onsemi.com
1 32
QFN32
G SUFFIX
CASE 488AM
MARKING
DIAGRAM
1
NB3F8L
3010C
AWLYYWWG
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information page 12 of this
data sheet.
© Semiconductor Components Industries, LLC, 2016
May, 2016 − Rev. 7
1
Publication Order Number:
NB3F8L3010C/D




NB3F8L3010C pdf, 반도체, 판매, 대치품
NB3F8L3010C
FUNCTION TABLES
Table 3. CLOCK ENABLE (SELx) FUNCTION TABLE
SEL[1:0] Input
Selected Input Clock
00 CLK0/CLK0
01 CLK1/CLK1
10 Crystal Osc Input
11 Crystal Osc Input
Table 5. DIFF IN/OUT TABLE (Diff or S.E.)
Input Condition
Output
CLK0/1; CLK0/1 = OPEN
Logic LOW
CLK0/1; CLK0/1 = GND
Undefined
CLK0/1 = HIGH; CLK0/1 = LOW
Logic HIGH
CLK0/1 = LOW; CLK0/1 = HIGH
Logic LOW
Table 4. CLOCK OUTPUT ENABLE (OE) FUNCTION
TABLE
OE Input
Q[9:0] Output
0 High Impedance
1 Outputs Enabled
Table 6. CRYSTAL CHARACTERISTICS
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Power
Min Typ Max
Fundamental
10 50
50
7
100
Unit
MHz
W
pF
mW
Table 7. ATTRIBUTES
Characteristic
ESD Protection
Human Body Model
Machine Model
Moisture Sensitivity (Note 2)
QFN32
Flammability Rating
Oxygen Index: 28 to 34
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
2. For additional information, see Application Note AND8003/D.
Value
>2 kV
200 V
Level 3
UL 94 V−0 @ 0.125 in
474 Devices
Table 8. MAXIMUM RATINGS (Note 3)
Symbol
Parameter
Condition
Rating
Unit
VDD,
VDDOn
VI
VO
TA
Tstg
θJA
Positive Power Supply
Input Voltage
XTAL_IN
Diff, SELx, OE Inputs
Output Voltage
Operating Temperature Range, Industrial
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient)
GND = 0 V
0 lfpm
500 lfpm
4.6 V
0 v VI v VDD
–0.5 v VI v VDD + 0.5
– 0.5 v VO v VDDOn + 0.5
−40 to +85
−65 to +150
31
27
V
V
_C
_C
_C/W
θJC Thermal Resistance (Junction−to−Case)
(Note 3)
12 _C/W
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power).
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NB3F8L3010C 전자부품, 판매, 대치품
NB3F8L3010C
PARAMETER MEASUREMENT INFORMATION
VDD = +1.65 V ±5%
VDDOn = VDD = +1.65 V ±5%
SCOPE
LVCMOS
Qx
Z = 50 W
50 W
GND = +1.65 V ±5%
3.3 V Core / 3.3 V Output Load AC Test Circuit
(Terminating to VDDOn/2)
VDD = +1.25 V ±5%
VDDOn = VDD = +1.25 V ±5%
SCOPE
LVCMOS
Qx
Z = 50 W
50 W
GND = +1.25 V ±5%
2.5 V Core / 2.5 V Output Load AC Test Circuit
(Terminating to VDDOn/2)
VDD = +2.05 V ±5%
VDDOn = +1.25 V ±5%
SCOPE
VDD = +2.4 V ±5%
VDDOn = +0.9 V ±0.1 V
SCOPE
LVCMOS
Qx
Z = 50 W
GND = +1.25 V ±5%
50 W
LVCMOS
Qx
Z = 50 W
GND = +0.9 V ±0.1 V
50 W
3.3 V Core / 2.5 V Output Load AC Test Circuit
(Terminating to VDDOn/2)
VDD = +2.55 V ±5%
VDDOn = +0.75 V ±0.15 V
SCOPE
3.3 V Core / 1.8 V Output Load AC Test Circuit
(Terminating to VDDOn/2)
VDD = +1.6 V ±5%
VDDOn = +0.9 V ±0.1 V
SCOPE
LVCMOS
Qx
Z = 50 W
LVCMOS
Qx
Z = 50 W
GND = +0.75 V ±0.15 V
50 W
GND = +0.9 V ±0.1 V
50 W
3.3 V Core / 1.5 V Output Load AC Test Circuit
(Terminating to VDDOn/2)
VDD = +1.75 V ±5%
VDDOn = +0.75 V ±0.15 V
2.5 V Core / 1.8 V Output Load AC Test Circuit
(Terminating to VDDOn/2)
SCOPE
LVCMOS
Qx
Z = 50 W
GND = +0.75 V ±0.5 V
50 W
2.5 V Core / 1.5 V Output Load AC Test Circuit
(Terminating to VDDOn/2)
Figure 3. Operational Supply and Termination Test Conditions
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NB3F8L3010C

3.3V / 2.5V / 1.8V / 1.5V 3:1:10 LVCMOS Fanout Buffer

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