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PDF NB3N853501E Data sheet ( Hoja de datos )
| Número de pieza | NB3N853501E | |
| Descripción | 3.3V LVTTL/LVCMOS 2:1 MUX to 4 LVPECL Differential Clock Fanout Buffer Outputs | |
| Fabricantes | ON Semiconductor | |
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NB3N853501E
3.3 V LVTTL/LVCMOS 2:1
MUX to 4 LVPECL
Differential Clock Fanout
Buffer Outputs with Clock
Enable and Clock Select
Description
The NB3N853501E is a pure 3.3 V supply 2:1:4 clock distribution
fanout buffer. Input MUX selects one of two LVCMOS/LVTTL CLK
lines by the CLK_SEL pin (HIGH for CLK1, LOW for CLK0) using
LVCMOS/LVTTL levels. Outputs are LVPECL levels and are
synchronously enabled by CLK_EN using LVCMOS/LVTTL levels
(HIGH to enable outputs, LOW to disable output).
Features
• Four differential LVPECL Outputs
• Two Selectable LVCMOS/LVTTL CLOCK Inputs
• Up to 266 MHz Clock Operation
• Output to Output Skew: 30 ps (Max.)
• Device to Device Skew 250 ps (Max.)
• Propagation Delay 2.0 ns (Max.)
• Operating range: VCC = 3.3 ±5% V( 3.135 to 3.465 V)
• Additive Phase Jitter, RMS: 62 fs (Typ)
• Synchronous Clock Enable Control
• Industrial Temp. Range (−40°C to 85°C)
• Pb−Free TSSOP20 Package
• These are Pb−Free Devices
http://onsemi.com
MARKING
DIAGRAM
TSSOP−20
DT SUFFIX
CASE 948E
NB3N
501E
ALYWG
G
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
Figure 1. Simplified Logic Diagram
© Semiconductor Components Industries, LLC, 2011
November, 2011 − Rev. 2
1
Publication Order Number:
NB3N853501E/D
1 page  
NB3N853501E
Table 6. AC CHARACTERISTICS VCC = 3.3 ±5% V (3.135 to 3.465 V), GND = 0 V, TA = −40°C to +85°C (Note 6)
Symbol
Characteristic
Min Typ Max
Unit
FMAX
tPD
tSKEWDC
tSKEWO−O
tSKEWD−D
tJIT
Maximum Operating Frequency
Propagation Delay
Duty Cycle Skew same path similar conditions at 50 MHz
Output to Output Skew Within A Device
Device−to−Device Skew similar path and conditions
Additive Phase Noise Jitter (RMS) @ 155.52 MHz (Integrated from 12 kHz to
20 MHz) See Figure 6.
0 266 MHz
0.9 2.0 ns
48 50 52 %
30 ps
250 ps
0.062
ps
tr/tf Output rise and fall times @ 266 MHz (20% and 80% points)
240 700 ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
6. Outputs terminated 50 W to VCC − 2.0 V, see Figure 4. Input levels of 0.8 V and 2.4 V unless stated otherwise. Measured from Input Midpoint
(VDD/2) to differential Output crosspoints, see Figure 5.
Figure 4. Typical Test Setup and Termination for Evaluation. The VCC of 2.0 V and VEE of −1.3 ±0.165 V Split
supply allows a direct connection to an oscilloscope 50 W impedance input module. Also reference AND8020.
http://onsemi.com
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