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부품번호 5100 기능
기능 Memory Controller Hub Chipset
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5100 데이터시트, 핀배열, 회로
Intel® 5100 Memory Controller Hub
Chipset
Datasheet
July 2009
Revision 005US
Order Number: 318378-005US




5100 pdf, 반도체, 판매, 대치품
Intel® 5100 MCH Chipset—Contents
3.6 Intel® 5100 Memory Controller Hub Chipset Fixed Memory Mapped Registers ............74
3.7 Detailed Configuration Space Maps.......................................................................76
3.8 Register Definitions ............................................................................................92
3.8.1 PCI Standard Registers............................................................................92
3.8.1.1 VID - Vendor Identification Register .............................................93
3.8.1.2 DID - Device Identification Register .............................................93
3.8.1.3 RID - Revision Identification Register ...........................................93
3.8.1.4 CCR - Class Code Register ..........................................................95
3.8.1.5 HDR - Header Type Register .......................................................96
3.8.1.6 SVID - Subsystem Vendor Identification Register...........................96
3.8.2 SID - Subsystem Identity ........................................................................97
3.8.3 Address Mapping Registers ......................................................................97
3.8.3.1 PAM0 - Programmable Attribute Map Register 0.............................98
3.8.3.2 PAM1 - Programmable Attribute Map Register 1.............................98
3.8.3.3 PAM2 - Programmable Attribute Map Register 2.............................99
3.8.3.4 PAM3 - Programmable Attribute Map Register 3.............................99
3.8.3.5 PAM4 - Programmable Attribute Map Registers 4 ......................... 100
3.8.3.6 PAM5 - Programmable Attribute Map Register 5........................... 101
3.8.3.7 PAM6 - Programmable Attribute Map Register 6........................... 101
3.8.3.8 SMRAMC - System Management RAM Control Register ................. 102
3.8.3.9 EXSMRC - Extended System Management RAM Control Register .... 102
3.8.3.10 EXSMRTOP - Extended System Management RAM Top Register ..... 103
3.8.3.11 EXSMRAMC - Expansion System Management RAM Control Register ....
104
3.8.3.12 HECBASE - PCI Express* Extended Configuration Base Address Register
104
3.8.4 Interrupt Redirection Registers ............................................................... 104
3.8.4.1 REDIRCTL - Redirection Control Register .................................... 104
3.8.4.2 REDIRBUCKETS - Redirection Bucket Number Register ................. 105
3.8.5 Boot and Reset Registers ....................................................................... 105
3.8.5.1 SYRE - System Reset Register................................................... 105
3.8.5.2 CPURSTCAPTMR: CPU Reset Done Cap Latency Timer .................. 106
3.8.5.3 POC - Power-On Configuration Register ...................................... 107
3.8.5.4 SPAD[3:0] - Scratch Pad Registers ............................................ 108
3.8.5.5 SPADS[3:0] - Sticky Scratch Pad............................................... 108
3.8.5.6 BOFL[3:0] - Boot Flag Register ................................................. 108
3.8.6 Control and Interrupt Registers .............................................................. 108
3.8.6.1 PROCENABLE: Processor Enable Global Control............................ 108
3.8.6.2 FSBC1: Processor Bus Controller ............................................... 109
3.8.6.3 FSBS[1:0] - Processor Bus Status Register ................................. 109
3.8.6.4 XTPR[15:0] - External Task Priority Register ............................... 109
3.8.7 PCI Express* Device Configuration Registers ............................................ 110
3.8.8 PCI Express* Header............................................................................. 112
3.8.8.1 PEXCMD[7:2,0]- Command Register .......................................... 113
3.8.8.2 PEXSTS[7:2,0] - Status Register ............................................... 114
3.8.8.3 CLS[7:2,0] - Cache Line Size .................................................... 116
3.8.8.4 PRI_LT[7:2,0] - Primary Latency Timer ...................................... 116
3.8.8.5 BIST[7:2,0] - Built-In Self-test ................................................. 116
3.8.8.6 BAR0[7:2,0] - Base Address Register 0 ...................................... 116
3.8.8.7 BAR1[7:2,0] - Base Address Register 1 ...................................... 116
3.8.8.8 EXP_ROM[0]: Expansion ROM Registers ..................................... 117
3.8.8.9 PBUSN[7:2] - Primary Bus Number............................................ 117
3.8.8.10 SBUSN[7:2] - Secondary Bus Number........................................ 117
3.8.8.11 SUBUSN[7:2] - Subordinate Bus Number ................................... 117
3.8.8.12 SEC_LT[7:2] - Secondary Latency Timer .................................... 118
3.8.8.13 IOBASE[7:2] - I/O Base Register............................................... 118
3.8.8.14 IOLIM[7:2] - I/O Limit Register ................................................. 118
3.8.8.15 SECSTS[7:2] - Secondary Status............................................... 119
Intel® 5100 Memory Controller Hub Chipset
Datasheet
4
July 2009
Order Number: 318378-005US

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5100 전자부품, 판매, 대치품
Contents—Intel® 5100 MCH Chipset
3.10
3.11
3.9.2 Memory Throttling Control Registers ....................................................... 188
3.9.2.1 GBLACT: Global Activation Throttle Register ............................... 189
3.9.2.2 THRTSTS[1:0]: Throttling Status Register .................................. 189
3.9.2.3 THRTHIGH: Thermal Throttle High Register ................................ 190
3.9.2.4 THRTLOW: Thermal Throttle Low Register .................................. 191
3.9.3 Memory Gearing Registers ..................................................................... 191
3.9.3.1 DDRFRQ: DDR Frequency Ratio ................................................ 191
3.9.3.2 MEMTOHOSTGRCFG0: MEM to Host Gear Ratio Configuration 0 ..... 192
3.9.3.3 MEMTOHOSTGRCFG1: MEM to Host Gear Ratio Configuration 1 ..... 192
3.9.3.4 MEMNDGRCFG0: MEM Next Data Gear Ratio Configuration 0......... 193
3.9.3.5 MEMNDGRCFG1: MEM Next Data Gear Ratio Configuration 1......... 193
3.9.3.6 HOSTTOMEMGRCFG0: Host to MEM Gear Ratio Configuration 0 ..... 194
3.9.3.7 HOSTTOMEMGRCFG1: Host to MEM Gear Ratio Configuration 1 ..... 194
3.9.4 DRAM Timing Registers ......................................................................... 195
3.9.4.1 DRTA[1:0]: DRAM Timing Register A ......................................... 196
3.9.4.2 DRTB[1:0]: DDR Timing Register B ........................................... 197
3.9.4.3 DRPADCTL[1:0]: DRAM Pads Control Register............................. 197
3.9.5 Memory Map Registers .......................................................................... 198
3.9.5.1 TOLM - Top Of Low Memory ..................................................... 198
3.9.5.2 MIR[1:0]: Memory Interleave Range ......................................... 198
3.9.5.3 AMIR[1:0]: Adjusted Memory Interleave Range .......................... 199
3.9.6 Memory Error Registers......................................................................... 199
3.9.6.1 FERR_NF_MEM: MC First Non Fatal Errors .................................. 200
3.9.6.2 NERR_NF_MEM: MC Next Non-Fatal Errors ................................. 200
3.9.6.3 EMASK_MEM: MC Error Mask Register ....................................... 201
3.9.6.4 ERR0_MEM: MC Error 0 Mask Register ....................................... 202
3.9.6.5 ERR1_MEM: MC Error 1 Mask Register ....................................... 203
3.9.6.6 ERR2_MEM: MEM Error 2 Mask Register ..................................... 203
3.9.6.7 MCERR_MEM: MEM MCERR Mask Register .................................. 204
3.9.6.8 VALIDLOG[1:0]: Valid Log Markers ........................................... 205
3.9.6.9 NRECMEMA[1:0]: Non-Recoverable Memory Error Log Register A .. 205
3.9.6.10 NRECMEMB[1:0]: Non-Recoverable Memory Error Log Register B .. 205
3.9.6.11 REDMEMA[1:0]: Recoverable Memory Data Error Log Register A ... 206
3.9.6.12 REDMEMB[1:0]: Recoverable Memory Data Error Log Register B ... 206
3.9.6.13 RECMEMA[1:0]: Recoverable Memory Error Log Register A ........... 207
3.9.6.14 RECMEMB[1:0]: Recoverable Memory Error Log Register B........... 207
3.9.7 Sparing Registers ................................................................................. 208
3.9.7.1 SPCPC[1:0]: Spare Copy Control .............................................. 208
3.9.7.2 SPCPS[1:0]: Spare Copy Status................................................ 208
3.9.8 Memory RAS Registers .......................................................................... 209
3.9.8.1 RANKTHRESHOLD[1:0][5:0]: RANK Count Threshold ................... 209
3.9.8.2 CERRCNT[1:0]: Correctable Error Count .................................... 210
3.9.8.3 CERRCNT_EXT[1:0]: Correctable Error Count ............................. 210
3.9.8.4 BADRAM[1:0]: Bad DRAM Marker ............................................. 211
3.9.8.5 BADCNT[1:0]: Bad DRAM Counter............................................. 211
3.9.9 Memory Control Debug Registers............................................................ 212
3.9.9.1 MEM[1:0]EINJMSK0: Memory Error Injection Mask0 Register ........ 212
3.9.9.2 MEM[1:0]EINJMSK1: Memory Error Injection Mask1 Register ........ 212
3.9.9.3 MEMEINJADDRMAT: Error Injection Address Match Register.......... 213
3.9.9.4 MEMEINJADDRMSK: Error Injection Address Mask Register........... 213
3.9.10 Memory Interface Control ...................................................................... 213
3.9.10.1 DSRETC[1:0]: DRAM Self-Refresh Extended Timing and Control .... 213
3.9.11 Serial Presence Detect Registers ............................................................ 214
3.9.11.1 SPDDATA - Serial Presence Detect Status Register ...................... 214
3.9.11.2 SPDCMD: Serial Presence Detect Command Register ................... 214
DMA Engine Configuration Registers .................................................................. 216
CB_BAR MMIO Registers .................................................................................. 217
3.11.1 PEXCMD: PCI Command Register ........................................................... 220
July 2009
Order Number: 318378-005US
Intel® 5100 Memory Controller Hub Chipset
Datasheet
7

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