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Z2V56S20BTP 데이터시트 PDF




Mezza에서 제조한 전자 부품 Z2V56S20BTP은 전자 산업 및 응용 분야에서
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부품번호 Z2V56S20BTP 기능
기능 256Mb Synchronous DRAM
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Z2V56S20BTP 데이터시트, 핀배열, 회로
北京亿芯伟业电子技术有限公司 电话:010-8287 3941/42/43/44 传真:010-8287 3945 http://www.echip.com.cn
256Mb Synchronous DRAM Specification
Z2V56S20BTP
Z2V56S30BTP
Z2V56S40BTP
Deutron Electronics Corp.
8F, 68, SEC. 3, NANKING E. RD., TAIPEI 104,
TAIWAN, R. O. C.
TEL : 886-2-2517-7768
FAX : 886-2-2517-4575
http: // www.deutron.com.tw




Z2V56S20BTP pdf, 반도체, 판매, 대치품
256Mb Synchronous DRAM北京亿芯伟业电子技术有限公司 电话:010-8287 3941/42/43/44 传真:010-8287 3945 http://www.echip.com.cn
Z2V56S20BTP (4-BANK x 16,777,216-WORD x 4-BIT)
Z2V56S30BTP (4-BANK x 8,388,608-WORD x 8-BIT)
Z2V56S40BTP (4-BANK x 4,194,304-WORD x 16-BIT)
PIN CONFIGURATION (TOP VIEW)
Vdd Vdd
NC DQ0
VddQ VddQ
NC NC
DQ0 DQ1
VssQ VssQ
NC NC
NC DQ2
VddQ VddQ
NC NC
DQ1 DQ3
VssQ VssQ
NC NC
Vdd Vdd
NC NC
/WE /WE
/CAS /CAS
/RAS /RAS
/CS /CS
BA0 BA0
BA1 BA1
A10/AP A10/AP
A0 A0
A1 A1
A2 A2
A3 A3
Vdd Vdd
Vdd
DQ0
VddQ
DQ1
DQ2
VssQ
DQ3
DQ4
VddQ
DQ5
DQ6
VssQ
DQ7
Vdd
DQML
/WE
/CAS
/RAS
/CS
BA0
BA1
A10/AP
A0
A1
A2
A3
Vdd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
X4
X8
X16
54 Vss
Vss
53 DQ15 DQ7
52 VssQ VssQ
51 DQ14 NC
50 DQ13 DQ6
49 VddQ VddQ
48 DQ12 NC
47 DQ11 DQ5
46 VssQ VssQ
45 DQ10 NC
44 DQ9 DQ4
43 VddQ VddQ
42 DQ8 NC
41 Vss
Vss
40 NC
NC
39 DQMU DQM
38 CLK
CLK
37 CKE CKE
36 A12
A12
35 A11
A11
34 A9
A9
33 A8
A8
32 A7
A7
31 A6
A6
30 A5
A5
29 A4
A4
28 Vss
Vss
Vss
NC
VssQ
NC
DQ3
VddQ
NC
NC
VssQ
NC
DQ2
VddQ
NC
Vss
NC
DQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
Vss
CLK
CKE
/CS
/RAS
/CAS
/WE
DQ0-15
: Master Clock
: Clock Enable
: Chip Select
: Row Address Strobe
: Column Address Strobe
: Write Enable
: Data I/O
DQM, DQMU/L : Output Disable / Write Mask
A0-12
: Address Input
BA0,1
: Bank Address Input
Vdd : Power Supply
VddQ
: Power Supply for Output
Vss : Ground
VssQ
: Ground for Output
Jan.2004
Page- 2
Rev.1.1

4페이지










Z2V56S20BTP 전자부품, 판매, 대치품
256Mb Synchronous DRAM北京亿芯伟业电子技术有限公司 电话:010-8287 3941/42/43/44 传真:010-8287 3945 http://www.echip.com.cn
Z2V56S20BTP (4-BANK x 16,777,216-WORD x 4-BIT)
Z2V56S30BTP (4-BANK x 8,388,608-WORD x 8-BIT)
Z2V56S40BTP (4-BANK x 4,194,304-WORD x 16-BIT)
BASIC FUNCTIONS
The Z2V56S20 , 30 and 40 BTP provides basic functions,
bank (row) activate, burst read / write, bank (row) precharge,
and auto / self refresh.
Each command is defined by control signals of /RAS,
/CAS and /WE at CLK rising edge. In addition to 3 signals,
/CS ,CKE and A10 are used as chip select, refresh opt ion,
and precharge option, respectively .
To know the detailed definition of commands,
please see the command truth table.
CLK
/CS
/RAS
/CAS
/WE
CKE
A10
Chip Select : L=select, H=deselect
Command
Command
define basic command
Command
Refresh Option @ refresh command
Precharge Option @ precharge or read/write command
Activate (ACT) [/RAS =L, /CAS =/WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read (READ) [/RAS =H, /CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA.
First output data appears after /CAS latency. When A10 =H at this command,
the bank is deactivated after the burst read (auto-precharge, READA).
Write (WRITE) [/RAS =H, /CAS =/WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total
data length to be written is set by burst length. When A10 =H at this command,
the bank is deactivated after the burst write (auto-precharge, WRITEA).
Precharge (PRE) [/RAS =L, /CAS =H, /WE =L]
PRE command deactivates the active bank indicated by BA. This com-
mand also terminates burst read / write operation. When A10 =H at this
command, all banks are deactivated (precharge all, PREA ).
Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE =H]
REFA command starts auto-refresh cycle. Refresh address including bank
address are generated internally. After this command, the banks are
precharged automatically.
Jan.2004
Page- 5
Rev.1.1

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Z2V56S20BTP

256Mb Synchronous DRAM

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