A3V28S40JTP Datasheet PDF - Zentel
| Part Number | A3V28S40JTP | |
| Description | 128M Single Data Rate Synchronous DRAM | |
| Manufacturers | Zentel | |
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A3V28S40JTP
128M Single Data Rate Synchronous DRAM
128Mb Synchronous DRAM Specification
A3V28S40JTP
Zentel Electronics Corp.
Revision 1.0
Oct., 2013
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A3V28S40JTP
128M Single Data Rate Synchronous DRAM
Pin Descriptions
SYMBOL
TYPE
DESCRIPTION
CLK
CKE
Input
Input
Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive
edge of CLK. CLK also increments the internal burst counter and controls the output registers.
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. Deactivating the
clock provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle),
ACTIVE POWER-DOWN (row active in any bank), or CLOCK SUSPEND operation (burst /
access in progress). CKE is synchronous except after the device enters self refresh mode, where
CKE becomes asynchronous until after exiting the same mode. The input buffers, including CLK,
are disabled during self refresh mode, providing low standby power. CKE may be tied HIGH.
Chip Select: /CS enables (registered LOW) and disables (registered HIGH) the command
decoder. All commands are masked when /CS is registered HIGH. /CS provides for external
/CS
Input
bank selection on systems with multiple banks. /CS is considered part of the command code.
/CAS,
/RAS,
/WE
LDQM,
UDQM,
Input
Input
Command Inputs: /CAS, /RAS, and /WE (along with /CS) define the command being entered.
Input / Output Mask: DQM is sampled HIGH and is an input mask signal for write accesses and
an output disable signal for read accesses. Input data is masked during a WRITE cycle. The
output buffers are placed in a High-Z state (two-clock latency) when during a READ cycle. LDQM
corresponds to DQ0–DQ7, UDQM corresponds to DQ8–DQ15.
BA0, BA1
A0–A11
Input
Input
Bank Address Input(s): BA0 and BA1 define to which bank the ACTIVE, READ, WRITE or
PRECHARGE command is being applied.
A0-11 specify the Row / Column Address in conjunction with BA0,1. The Row Address is
specified by A0-11. The Column Address is specified by A0-8. A10 is also used to indicate
precharge option. When A10 is high at a read / write command, an auto precharge is performed.
When A10 is high at a precharge command, all banks are precharged.
DQ0–DQ15
NC
VddQ
VssQ
Vdd
Vss
I/O
–
Supply
Supply
Supply
Supply
Data Input / Output: Data bus.
Internally Not Connected: These could be left unconnected, but it is recommended they be
connected or VSS.
Data Output Power: Provide isolated power to output buffers for improved noise immunity.
Data Output Ground: Provide isolated ground to output buffers for improved noise immunity.
Power for the input buffers and core logic.
Ground for the input buffers and core logic.
Revision 1.0
Page 4/39
Oct., 2013
Preview 5 Page |
Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for A3V28S40JTP electronic component. |
| Information | Total 30 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
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