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A3S28D30FTP 데이터시트 PDF




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부품번호 A3S28D30FTP 기능
기능 128M Double Data Rate Synchronous DRAM
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A3S28D30FTP 데이터시트, 핀배열, 회로
A3S28D30FTP
A3S28D40FTP
128M Double Data Rate Synchronous DRAM
128Mb DDR SDRAM Specification
A3S28D30FTP
A3S28D40FTP
Zentel Electronics Corp.
Revision 1.0
Apr., 2010




A3S28D30FTP pdf, 반도체, 판매, 대치품
A3S28D30FTP
A3S28D40FTP
128M Double Data Rate Synchronous DRAM
PIN FUNCTION
SYMBOL
CLK, /CLK
CKE
/CS
/RAS, /CAS, /WE
A0-11
BA0,1
TYPE
Input
Input
Input
Input
Input
Input
DESCRIPTION
Clock: CLK and /CLK are differential clock inputs. All address and control
input signals are sampled on the crossing of the positive edge of CLK and
negative edge of /CLK. Output (read) data is referenced to the crossings of
CLK and /CLK (both directions of crossing).
Clock Enable: CKE controls Power Down and Self Refresh.
Taking CKE LOW provides Precharge Power Down or Self Refresh (all banks idle),
or Active Power Down (row active in any bank).
Taking CKE HIGH provides Power Down exit or Self Refresh exit.
After Self Refresh is started, CKE becomes asynchronous input.
Power Down and Self Refresh is maintained as long as CKE is LOW.
Chip Select: When /CS is HIGH, any command means No Operation.
Combination of /RAS, /CAS, /WE defines basic commands.
A0-11 specify the Row / Column Address in conjunction with BA0,1. The
Row Address is specified by A0-11. The Column Address is specified by
A0-9(x8) and A0-8(x16). A10 is also used to indicate precharge
option. When A10 is HIGH at a Read / Write command, an Auto Precharge
is performed. When A10 is HIGH at a Precharge command, all banks are precharged.
Bank Address: BA0,1 specifies one of four banks to which a command is applied.
BA0,1 must be set with Active, Precharge, Read, Write commands.
DQ0-7 (x8),
Input / Output Data Input/Output: Data bus
DQ0-15 (x16),
DQS (x8)
Input / Output
UDQS, LDQS (x16)
Data Strobe: Output with read data, input with write data. Edge-aligned
with read data, centered in write data. Used to capture write data.
For the x16, LDQS corresponds to the data on DQ0-DQ7; UDQS
correspond to the data on DQ8-DQ15
DM (x8)
UDM, LDM (x16)
Input
Input Data Mask: DM is an input mask signal for write data. Input data
is masked when DM is sampled HIGH along with that input data
during a write access. DM is sampled on both edges of DQS.
Although DM pins are input only, the DM loading matches the DQ
and DQS loading. For the x16, LDM corresponds to the data on DQ0-DQ7;
UDM corresponds to the data on DQ8-DQ15.
Vdd, Vss
Power Supply Power Supply for the memory array and peripheral circuitry.
VddQ, VssQ
Power Supply VddQ and VssQ are supplied to DQ, DQS buffers.
VREF
Input
SSTL_2 reference voltage.
Revision 1.0
Page 3 / 39
Apr., 2010

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A3S28D30FTP 전자부품, 판매, 대치품
A3S28D30FTP
A3S28D40FTP
128M Double Data Rate Synchronous DRAM
BASIC FUNCTIONS
The A3S28D30/40FTP provides basic functions, Active, Read / Write, Precharge, and Auto / Self
Refresh, Mode Register Set, Burst Terminate. Each command is defined by control signals of
/RAS, /CAS and /WE at CLK rising edge. In addition to 3 signals, /CS , CKE and A10 are used as
chip select, refresh option, and precharge option, respectively. To know the detailed definition of
commands, please see the command truth table.
/CLK
CLK
/CS
Chip Select : L=select, H=deselect
/RAS
Command
/CAS
Command
define basic commands
/WE
Command
CKE
Refresh option @ Refresh command
A10 Precharge option @ Precharge or Read/Write command
Deselect (DESEL) [/CS = H, /RAS = X, /CAS = X, /WE = X]
DESEL command prevents new commands from being executed. Operations already in progress
are not affected.
No Operation (NOP) [/CS = L, /RAS = H, /CAS = H, /WE = H]
NOP command prevents unwanted commands from being registered. NOP command is effectively
the same as DESEL command. Operations already in progress are not affected.
Mode Register Set (MRS) [/CS = L, /RAS = L, /CAS = L, /WE = L]
MRS command loads the mode registers via inputs BA0,1, and A0-A11. The MRS command can only
be issued when all banks are idle and no bursts are in progress, and a subsequent executable command
cannot be issued until tMRD is met.
Active (ACT) [/CS = L, /RAS = L, /CAS = H, /WE = H]
ACT command activates a row in an idle bank indicated by BA.
Read (READ) [/CS = L, /RAS = H, /CAS = L, /WE = H]
READ command starts burst read from the active bank indicated by BA. First output data appears after
/CAS latency. When A10 = H at this command, the bank is deactivated after the burst read (Read with
Auto Precharge, READA).
Write (WRITE) [/CS = L, /RAS = H, /CAS = L, /WE = L]
WRITE command starts burst write to the active bank indicated by BA. Total data length to be written
is set by burst length. When A10 = H at this command, the bank is deactivated after the burst write
(Write with Auto Precharge, WRITEA).
Revision 1.0
Page 6 / 39
Apr., 2010

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A3S28D30FTP

128M Double Data Rate Synchronous DRAM

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