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PDF OTA5182A Data sheet ( Hoja de datos )
| Número de pieza | OTA5182A | |
| Descripción | System-On-Chip for small size TFT-LCDs | |
| Fabricantes | ORISE | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de OTA5182A (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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OTA5182A
System-On-Chip for small size
TFT-LCDs
Preliminary
Mar. 10, 2009
Version 0.5
ORISE Technology reserves the right to change this documentation without prior notice. Information provided by ORISE Technology is believed to be
accurate and reliable. However, ORISE Technology makes no warranty for any errors which may appear in this document. Contact ORISE Technology to
obtain the latest version of device specifications before placing your order. No responsibility is assumed by ORISE Technology for any infringement of patent
or other rights of third parties which may result from its use. In addition, ORISE Technology products are not authorized for use as critical components in life
support devices/ systems or aviation devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to
the user, without the express written approval of ORISE Technology.
1 page  
Preliminary
OTA5182A
5. SIGNAL DESCRIPTIONS
SYMBOL
TYPE
DESCRIPTION
SERIAL COMMUNICATION INTERFACE
SCL
CSB
SDA
I Serial communication clock input.
I Serial communication chip select.
I Serial communication data input.
TIMING CONTROLLER (TCON)
DCLK
HSYNC
VSYNC
STB
GRB
D0[7..0]
I Clock signal. Data are latched onto the Line Latch on the positive edge of DCLK.
I Horizontal sync input. Negative polarity.
I Vertical sync input. Negative polarity.
Standby mode (active low).
I STB = “L”: T-CON, source driver and DC-DC converter are off. All outputs are High-Z.
STB = “H” Normal operation. (Default setting)
Global reset pin (active low).
I
GRB = “L”: The controller is reset; charge pump and DCDC are off. Bypass Serial Settings.
GRB = “H”: Global Reset controlled by serial register GRB. (Default setting)
Data input (DIN). 8-bit color sub-pixel (R, G or B).
I
D07: MSB; D00: LSB.
SOURCE DRIVER
S1~S480
GATE DRIVER
G0~G241
VCOM GENERATOR
FRP
VCAC
VCOMDC
POWER SUPPLY
VDD
VDD_25V
VDDIO
GND
AGND
VDDA
VDD3
VGH
VGL
C1P/N
C2P/N
C3P/N
C4P/N
O
O
O
PO
O
P
PO
P
P
P
PO
PO
PO
PO
C
Source driver output signals.
Gate driver output signals.
Frame polarity output. This signal is toggling between VCAC and GND.
Defines the amplitude of the VCOM swing (VCOM_AC value).
VCOM DC level output.
Charge Pump power supply.
Digital power supply.
Input I/O power supply
Digital ground.
Analog ground for source driver.
Intermediate voltage for Charge Pump.
Intermediate voltage for Charge Pump.
Positive power supply for gate driver outputs: +18V
Negative Low power supply for gate driver outputs: -6V
Pins to connect capacitors for power circuitry.
DC TO DC CONVERTER
DRV
FB
O Gate signal for the power transistor of the boost converter.
I Main boost regulator feedback input.
© ORISE Technology Co., Ltd.
Proprietary & Confidential
5
MAR. 10, 2009
Preliminary Version: 0.5
5 Page 
6.3.9. S8 settings
Adress
1000
Bit
[4:0]
Description
Bit[4:0](DDL)
Horizontal Data start delay selection.
Bit[4:0]
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
DDL function
NO.
0
+1
+2
+3
+4
+5
+6
+7
+8
+9
+10
+11
+12
+13
+14
+15
-1
-2
-3
-4
-5
-6
-7
-8
-9
-10
-11
-12
-13
-14
-15
-16
unit
DCLK
Preliminary
OTA5182A
Default
xxx0_0000b
© ORISE Technology Co., Ltd.
Proprietary & Confidential
11
MAR. 10, 2009
Preliminary Version: 0.5
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet OTA5182A.PDF ] | |
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