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PDF PHU77NQ03T Data sheet ( Hoja de datos )
| Número de pieza | PHU77NQ03T | |
| Descripción | N-channel TrenchMOS FET | |
| Fabricantes | NXP Semiconductors | |
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PHD/PHU77NQ03T
N-channel TrenchMOS FET
Rev. 01 — 28 November 2006
Product data sheet
1. Product profile
1.1 General description
N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using
TrenchMOS technology.
1.2 Features
I Fast switching
I Low thermal resistance
1.3 Applications
I DC-to-DC converters
I Computer motherboard
1.4 Quick reference data
I VDS ≤ 25 V
I RDSon ≤ 9.5 mΩ
I ID ≤ 75 A
I QGD = 3.2 nC (typ)
2. Pinning information
Table 1. Pinning
Pin Description
1 gate (G)
2 drain (D)
3 source (S)
mb mounting base; connected to
drain (D)
Simplified outline
[1]
mb
2
13
SOT428 (DPAK)
[1] It is not possible to make a connection to pin 2 of the SOT428 package.
Symbol
mb
D
123
SOT533 (IPAK)
G
mbb076 S
1 page  
NXP Semiconductors
PHD/PHU77NQ03T
N-channel TrenchMOS FET
6. Characteristics
Table 5. Characteristics
Tj = 25 °C unless otherwise specified.
Symbol Parameter
Conditions
Static characteristics
V(BR)DSS drain-source breakdown
voltage
VGS(th) gate-source threshold voltage
IDSS drain leakage current
IGSS
RG
RDSon
gate leakage current
gate resistance
drain-source on-state
resistance
Dynamic characteristics
ID = 250 µA; VGS = 0 V
Tj = 25 °C
Tj = −55 °C
ID = 1 mA; VDS = VGS; see Figure 9 and 10
Tj = 25 °C
Tj = 175 °C
Tj = −55 °C
VDS = 25 V; VGS = 0 V
Tj = 25 °C
Tj = 175 °C
VGS = ±20 V; VDS = 0 V
f = 1 MHz
VGS = 10 V; ID = 25 A; see Figure 6 and 8
Tj = 25 °C
Tj = 175 °C
QG(tot)
QGS
total gate charge
gate-source charge
ID = 25 A; VDS = 12 V; VGS = 10 V;
see Figure 11 and 12
QGS1 pre-VGS(th) gate-source charge
QGS2 post-VGS(th) gate-source charge
QGD
gate-drain charge
VGS(pl) gate-source plateau voltage
QG(tot) total gate charge
ID = 0 A; VDS = 0 V; VGS = 4.5 V
Ciss input capacitance
Coss output capacitance
VGS = 0 V; VDS = 12 V; f = 1 MHz;
see Figure 14
Crss reverse transfer capacitance
Ciss input capacitance
VGS = 0 V; VDS = 0 V; f = 1 MHz
td(on)
tr
turn-on delay time
rise time
VDS = 12 V; RL = 0.5 Ω; VGS = 10 V;
RG = 5.6 Ω
td(off)
turn-off delay time
tf fall time
Source-drain diode
VSD source-drain voltage
trr reverse recovery time
Qr recovered charge
IS = 25 A; VGS = 0 V; see Figure 13
IS = 20 A; dIS/dt = −100 A/µs; VGS = 0 V
Min Typ Max Unit
25 - - V
25 - - V
2.1 2.65 3.2 V
1.35 - - V
- - 3.65 V
- - 10 µA
- - 500 µA
- - 100 nA
- 1.2 - Ω
- 8.3 9.5 mΩ
- 15 17.1 mΩ
- 17.1 - nC
- 6 - nC
- 3.2 - nC
- 2.8 - nC
- 3.2 - nC
- 5- V
- 6.2 - nC
- 860 - pF
- 400 - pF
- 165 - pF
- 1200 - pF
- 8.3 - ns
- 7.6 - ns
- 24.8 - ns
- 6.6 - ns
- 0.9 1.2 V
- 34 - ns
- 12.5 - nC
PHD_PHU77NQ03T_1
Product data sheet
Rev. 01 — 28 November 2006
© NXP B.V. 2006. All rights reserved.
5 of 13
5 Page 
NXP Semiconductors
8. Revision history
Table 6. Revision history
Document ID
PHD_PHU77NQ03T_1
Release date
20061128
PHD/PHU77NQ03T
N-channel TrenchMOS FET
Data sheet status
Product data sheet
Change notice
-
Supersedes
-
PHD_PHU77NQ03T_1
Product data sheet
Rev. 01 — 28 November 2006
© NXP B.V. 2006. All rights reserved.
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