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부품번호 | FST16211 기능 |
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기능 | 24-Bit Bus Switch | ||
제조업체 | Fairchild Semiconductor | ||
로고 | |||
전체 8 페이지수
www.DataSheet4U.com
July 1997
Revised August 2000
FST16211
24-Bit Bus Switch
General Description
The Fairchild Switch FST16211 provides 24-bits of high-
speed CMOS TTL-compatible bus switching. The low on
resistance of the switch allows inputs to be connected to
outputs without adding propagation delay or generating
additional ground bounce noise.
The device is organized as a 12-bit or 24-bit bus switch.
When OE1 is LOW, the switch is ON and Port 1A is con-
nected to Port 1B. When OE2 is LOW, Port 2A is connected
to Port 2B. When OE1/2 is HIGH, a high impedance state
exists between the A and B Ports.
Features
s 4Ω switch connection between two ports
s Minimal propagation delay through the switch
s Low lCC
s Zero bounce in flow-through mode
s Control inputs compatible with TTL level
s Also packaged in plastic Fine Pitch Ball Grid Array
(FBGA)
Ordering Code:
Order Number Package Number
Package Description
FST16211GX
(Note 1)
BGA54A
Preliminary
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-195, 5.5mm Wide
[TAPE and REEL]
FST16211MEA
MS56A
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
FST16211MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Note 1: BGA package available in Tape and Reel only.
Logic Diagram
© 2000 Fairchild Semiconductor Corporation DS500037
www.fairchildsemi.com
AC Electrical Characteristics
TA = −40 °C to +85 °C,
Symbol
Parameter
CL = 50pF, RU = RD = 500Ω
VCC = 4.5 – 5.5V
VCC = 4.0V
Units
Conditions
Figure
No.
Min Max Min Max
tPHL,tPLH
Prop Delay Bus to Bus (Note 8)
0.25 0.25 ns VI = OPEN
Figures
1, 2
tPZH, tPZL
Output Enable Time
1.5 6.0
6.5 ns VI = 7V for tPZL
VI = OPEN for tPZH
Figures
1, 2
tPHZ, tPLZ
Output Disable Time
1.5 7.0
7.2 ns VI = 7V for tPLZ
VI = OPEN for tPHZ
Figures
1, 2
Note 8: This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the typical On
resistance of the switch and the 50pF load capacitance, when driven by an ideal voltage source (zero output impedance).
Capacitance (Note 9)
Symbol
Parameter
Typ
CIN Control Pin Input Capacitance
3
CI/O Input/Output Capacitance
6
Note 9: TA = +25°C, f = 1 MHz, Capacitance is characterized but not tested.
Max
Units
pF
pF
Conditions
VCC = 5.0V
VCC, OE = 5.0V
AC Loading and Waveforms
Note: Input driven by 50 Ω source terminated in 50 Ω
Note: CL includes load and stray capacitance
Note: Input PRR = 1.0 MHz, tW = 500 ns
FIGURE 1. AC Test Circuit
www.fairchildsemi.com
FIGURE 2. AC Waveforms
4
4페이지 Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD56
Technology Description
The Fairchild Switch family derives from and embodies Fairchild’s proven switch technology used for several years in its
74LVX3L384 (FST3384) bus switch product.
7 www.fairchildsemi.com
7페이지 | |||
구 성 | 총 8 페이지수 | ||
다운로드 | [ FST16211.PDF 데이터시트 ] |
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부품번호 | 상세설명 및 기능 | 제조사 |
FST16210 | 20-Bit Bus Switch | Fairchild Semiconductor |
FST16211 | 24-Bit Bus Switch | Fairchild Semiconductor |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |