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FST162861MTD 데이터시트 PDF




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부품번호 FST162861MTD 기능
기능 20-Bit Bus Switch with 25W Series Resistors in Outputs
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FST162861MTD 데이터시트, 핀배열, 회로
March 2000
Revised June 2005
FST162861
20-Bit Bus Switch with 25: Series Resistors in Outputs
General Description
The Fairchild Switch FST162861 provides 20-bits of high-
speed CMOS TTL-compatible bus switching. The low On
Resistance of the switch allows inputs to be connected to
outputs without adding propagation delay or generating
additional ground bounce noise.
The device is organized as a 10-bit or 20-bit bus switch.
When OE1 is LOW, the switch is ON and Port 1A is con-
nected to Port 1B. When OE2 is LOW, Port 2A is connected
to Port 2B. When OEX is HIGH, a high impedance state
exists between the A and B ports. The FST162861 has an
equivalent 25: series resistors to reduce signal-reflection
noise, eliminating the need for external terminating resis-
tors.
Features
s 25: switch connection between two ports.
s Minimal propagation delay through the switch.
s Low lCC.
s Zero bounce in flow-through mode.
s Control inputs compatible with TTL level.
Ordering Code:
Order Number
Package
Number
Package Description
FST162861MTD
(Note 1)
MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
FST162861MTDX_NL
(Note 2)
MTD48
Pb-Free 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
6.1mm Wide
Note 1: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Note 2: “_NL” indicates Pb-Free product (per JEDEC J-STD-020B). Device is available in Tape and Reel only.
© 2005 Fairchild Semiconductor Corporation DS500319
www.fairchildsemi.com




FST162861MTD pdf, 반도체, 판매, 대치품
AC Electrical Characteristics
Symbol
Parameter
tPHL,tPLH
Prop Delay Bus to Bus (Note 9)
TA 40 qC to 85 qC,
CL 50 pF, RU RD 500:
VCC 4.5 – 5.5V
VCC 4.0V
Min Max Min Max
1.25
1.25
Units
Conditions
ns VI OPEN
Figure
No.
Figures
1, 2
tPZH, tPZL
Output Enable Time
1.0 5.3
5.5 ns VI 7V for tPZL
VI OPEN for tPZH
Figures
1, 2
tPHZ, tPLZ
Output Disable Time
1.0 6.0
6.3 ns VI 7V for tPLZ
VI OPEN for tPHZ
Figures
1, 2
Note 9: This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the typical On
Resistance of the switch and the 50pF load capacitance, when driven by an ideal voltage source (zero output impedance).
Capacitance (Note 10)
Symbol
Parameter
Typ
CIN Control Pin Input Capacitance
3.5
CI/O Input/Output Capacitance OFF State
6.0
Note 10: TA 25qC, f 1 MHz, Capacitance is characterized but not tested.
AC Loading and Waveforms
Max
Units
pF
pF
Conditions
VCC 5.0V, VIN 0V
VCC, OE 5.0V, VIN 0V
Note: Input driven by 50: source terminated in 50:
Note: CL includes load and stray capacitance
Note: Input PRR 1.0 MHz, tW 500 ns
FIGURE 1. AC Test Circuit
www.fairchildsemi.com
FIGURE 2. AC Waveforms
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FST162861MTD

20-Bit Bus Switch with 25W Series Resistors in Outputs

Fairchild Semiconductor
Fairchild Semiconductor

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