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74HCT164 데이터시트 PDF




NXP Semiconductors에서 제조한 전자 부품 74HCT164은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

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부품번호 74HCT164 기능
기능 8-bit serial-in / parallel-out shift register
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74HCT164 데이터시트, 핀배열, 회로
74HC164; 74HCT164
8-bit serial-in, parallel-out shift register
Rev. 7 — 13 June 2013
Product data sheet
1. General description
The 74HC164; 74HCT164 is an 8-bit serial-in/parallel-out shift register. The device
features two serial data inputs (DSA and DSB), eight parallel data outputs (Q0 to Q7).
Data is entered serially through DSA or DSB and either input can be used as an active
HIGH enable for data entry through the other input. Data is shifted on the LOW-to-HIGH
transitions of the clock (CP) input. A LOW on the master reset input (MR) clears the
register and forces all outputs LOW, independently of other inputs. Inputs include clamp
diodes. This enables the use of current limiting resistors to interface inputs to voltages in
excess of VCC.
2. Features and benefits
Input levels:
For 74HC164: CMOS level
For 74HCT164: TTL level
Gated serial data inputs
Asynchronous master reset
Complies with JEDEC standard no. 7A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V.
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C.




74HCT164 pdf, 반도체, 판매, 대치품
NXP Semiconductors
74HC164; 74HCT164
8-bit serial-in, parallel-out shift register
5.2 Pin description
Table 2. Pin description
Symbol
Pin
DSA
1
DSB
2
Q0 to Q7
3, 4, 5, 6, 10, 11, 12, 13
GND
7
CP 8
MR 9
VCC 14
6. Functional description
Description
data input
data input
output
ground (0 V)
clock input (LOW-to-HIGH, edge-triggered)
master reset input (active LOW)
positive supply voltage
Table 3. Function table[1]
Operating
modes
Input
MR
Reset (clear)
L
Shift
H
H
H
H
CP
X
DSA
X
l
l
h
h
DSB
X
l
h
l
h
Output
Q0
L
L
L
L
H
Q1 to Q7
L to L
q0 to q6
q0 to q6
q0 to q6
q0 to q6
[1] H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition
q = lower case letters indicate the state of the referenced input one set-up time prior to the LOW-to-HIGH clock transition
= LOW-to-HIGH clock transition
7. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min Max Unit
VCC
IIK
IOK
IO
ICC
IGND
Tstg
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
VI < 0.5 V or VI > VCC + 0.5 V
VO < 0.5 V or VO > VCC + 0.5 V
0.5 V < VO < VCC + 0.5 V
0.5
[1] -
[1] -
-
-
50
65
+7
20
20
25
50
-
+150
V
mA
mA
mA
mA
mA
C
74HC_HCT164
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 13 June 2013
© NXP B.V. 2013. All rights reserved.
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74HCT164 전자부품, 판매, 대치품
NXP Semiconductors
74HC164; 74HCT164
8-bit serial-in, parallel-out shift register
10. Dynamic characteristics
Table 7. Dynamic characteristics
GND = 0 V; tr = tf = 6 ns; CL = 50 pF; test circuit see Figure 10; unless otherwise specified
Symbol Parameter Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max
Min
Max
74HC164
tpd propagation CP to Qn; see Figure 7 [1]
delay
VCC = 2.0 V
- 41 170 -
VCC = 4.5 V
- 15 34
-
VCC = 5.0 V; CL = 15 pF
- 12 -
-
VCC = 6.0 V
- 12 29
-
tPHL HIGH to LOW MR to Qn; see Figure 8
propagation
delay
VCC = 2.0 V
VCC = 4.5 V
- 39 140
- 14 28
-
-
VCC = 5.0 V; CL = 15 pF
- 11 -
-
VCC = 6.0 V
- 11 24
-
tt transition time see Figure 7
[2]
VCC = 2.0 V
- 19 75
-
VCC = 4.5 V
- 7 15
-
VCC = 6.0 V
- 6 13
-
tW pulse width CP HIGH or LOW;
see Figure 7
215
43
-
37
175
35
-
30
95
19
16
-
-
-
-
-
-
-
-
-
-
-
255 ns
51 ns
- ns
43 ns
210 ns
42 ns
- ns
36 ns
110 ns
22 ns
19 ns
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
MR LOW; see Figure 8
80 14
16 5
14 4
-
-
-
100
20
17
-
-
-
120
24
20
- ns
- ns
- ns
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
trec recovery time MR to CP; see Figure 8
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
tsu set-up time DSA, and DSB to CP;
see Figure 9
60 17
12 6
10 5
-
-
-
75
15
13
60 17
12 6
10 5
-
-
-
75
15
13
-
-
-
-
-
-
90
18
15
90
18
15
- ns
- ns
- ns
- ns
- ns
- ns
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
th
hold time
DSA, and DSB to CP;
see Figure 9
60 8
12 3
10 2
-
-
-
75
15
13
-
-
-
90
18
15
- ns
- ns
- ns
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
+4 6
+4 2
+4 2
-
-
-
4
4
4
-
-
-
4
4
4
- ns
- ns
- ns
74HC_HCT164
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 13 June 2013
© NXP B.V. 2013. All rights reserved.
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