PDF Si4706-C30 Data sheet ( Hoja de datos )

Número de pieza	Si4706-C30
Descripción	HIGH-PERFORMANCE FM RDS/RBDS RECEIVER
Fabricantes	Silicon Laboratories
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No Preview Available ! Si4706-C30 HIGH-PERFORMANCE FM RDS/RBDS RECEIVER Note: The Si4706-C30 requires a patch for production operation. See section “11. Additional Reference Resources” Features  Worldwide FM band support (76–108 MHz)  Advanced patented RDS/RBDS decoding engine  Outstanding RDS sensitivity  Leading RDS synchronization metrics  Highly reliable RDS decoder  RDS reception with FM mono broadcast  Received signal quality indicators  On-chip tuned resonance for embedded antenna support  FM multi-path detection and mitigation  FM Hi-cut control  Advanced FM stereo-mono blend  Automatic gain control (AGC)  Integrated FM LNA  Image-rejection mixer  Frequency synthesizer with integrated VCO  Low-IF direct conversion with no external ceramic filters  2.7 to 5.5 V supply voltage  Programmable reference clock  Stereo audio out  I2S Digital audio out  20-pin 3 x 3 mm QFN package Pb-free/RoHS compliant Applications  Cellular handsets  Portable media devices  In-car navigation systems  Dedicated data receiver  Personal navigation devices (PND)  GPS-enabled handsets and portable devices Description The high-performance Si4706-C30 FM RDS receiver provides the most advanced and flexible audio and RDS data processing available for portable devices today. The 100% CMOS IC integrates the complete FM and data receiver function from antenna to analog or digital audio and data out in a single 3 x 3 mm 20-pin QFN. Functional Block Diagram Half-wavelength antenna FMI Embedded antenna LPI RFGND 32.768 kHz (TYP) RCLK 2.7–5.5 V VDD LNA AGC 0/90 AFC REG XTAL OSC ADC PGA DSP ADC RSSI RDS CONTROL INTERFACE Si4706 DAC LOUT DAC ROUT GPO DCLK DOUT DFS Ordering Information: See page 29. Pin Assignments Si4706-GM (Top View) NC 1 20 19 18 17 16 FMI 2 15 DOUT RFGND 3 LPI 4 GND PAD 14 LOUT 13 ROUT RST 5 12 GND 6 7 8 9 10 11 VDD This product, its features, and/or its architecture is covered by one or more of the following patents, as well as other patents, pending and issued, both foreign and domestic: 7,127,217; 7,272,373; 7,272,375; 7,321,324; 7,355,476; 7,426,376; 7,471,940; 7,339,503; 7,339,504. Rev. 1.0 7/09 Copyright © 2009 by Silicon Laboratories Si4706-C30 Silicon Laboratories Confidential. Information contained herein is covered under non-disclosure agreement (NDA). 1 page Si4706-C30 Table 3. DC Characteristics (VDD = 2.7 to 5.5 V, VIO = 1.62 to 3.6 V, TA = –20 to 85 °C) Parameter Symbol Test Condition Min Typ FM Receiver to Line Output VDD Supply Current Supplies and Interface IFM Analog Output Mode — 21.4 Interface Supply Current IIO — 400 VDD Powerdown Current IDDPD — 10 VIO Powerdown Current High Level Input Voltage1 Low Level Input Voltage1 High Level Input Current1 Low Level Input Current1 High Level Output Voltage2 Low Level Output Voltage2 IIOPD VIH VIL IIH IIL VOH VOL SCLK, RCLK inactive VIN = VIO = 3.6 V VIN = 0 V, VIO = 3.6 V IOUT = 500 µA IOUT = –500 µA — 0.7 x VIO –0.3 –10 –10 0.8 x VIO — 1 — — — — — — Notes: 1. For input pins SCLK, SEN, SDIO, RST, RCLK, DCLK, DFS, GPO1, GPO2, and GPO3. 2. For output pins SDIO, DOUT, GPO1, GPO2, and GPO3. Max Unit 24 mA 600 20 10 VIO + 0.3 0.3 x VIO 10 10 µA µA µA V V µA µA — 0.2 x VIO V V Rev. 1.0 5 5 Page Si4706-C30 Table 8. Digital Audio Interface Characteristics (VDD = 2.7 to 5.5 V, VIO = 1.62 to 3.6 V, TA = –20 to 85 °C) Parameter DCLK Cycle Time DCLK Pulse Width High DCLK Pulse Width Low DFS Set-up Time to DCLK Rising Edge DFS Hold Time from DCLK Rising Edge DOUT Propagation Delay from DCLK Falling Edge Symbol Test Condition tDCT tDCH tDCL tSU:DFS tHD:DFS tPD:DOUT Min 26 10 10 5 5 0 Typ Max Unit — 1000 ns — — ns — — ns — — ns — — ns — 12 ns DCLK DFS DOUT tDCH tDCL tDCT tHD:DFS tSU:DFS tPD:OUT Figure 8. Digital Audio Interface Timing Parameters, I2S Mode Rev. 1.0 11 11 Page

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