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PDF CSS555C Data sheet ( Hoja de datos )
| Número de pieza | CSS555C | |
| Descripción | Micropower Timer | |
| Fabricantes | Custom Silicon Solutions | |
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Custom Silicon Solutions, Inc.
CSS555C
Micropower Timer (with Internal Timing Capacitor)
GENERAL PART DESCRIPTION
The CSS555C is a micropower version of the popular 555 timer IC. It features an operating current
under 5µA and a minimum supply voltage of 1.2V, making it ideal for battery-operated applications. A
six-decade programmable counter is included to allow generation of long timing delays. Configuration
data for the counter is held in EEPROM to maintain the standard pin count of eight. The analog circuits
are temperature compensated to provide excellent stability over a wide ambient temperature range. A
simple four-wire interface provides Read/Write access to the EEPROM. The CSS555C device includes
an internal precision timing capacitor (CTI). Its value is trimmed to 100pF ±1%.
Key Features
• Lowest power 555 timer (by > 10X)!
Active mode current < 5 µA
• Wide operating range
Wide supply range: 1.2V to 5.5V
Temperature range: -40°C to +85°C
• Internal 6 decade, programmable counter
Settings = 1, 10, 102, 103, 104, 105 & 106
Multiplies delay time by up to 106
Delay times from microseconds to days
• Internal 100pF, ±1% Timing Capacitor
User adjustable, 0.2pF resolution
• Pin-for-pin compatible with 555 series timers
Monostable or Astable operation
• Extremely low transient switching current
“Break-Before-Make” output driver
• Temperature stability – 0.005% per °C
Applications
• Portable & Battery-Powered Systems
• Precision Timing & Pulse Generation
• Ultra Long Period Delay Generation
• Single Cell Battery Applications
• Ultra Low Power Timers
• Pulse Width Modulation
• Low Cost, High Reliability Applications
Pin Configuration
GND
TRIGGER
OUTPUT
RESET
1
2
3
4
8 V+
7 DISCHARGE
6 THRESHOLD
5 CONTROL V
PDIP or SOIC
Figure 1
Typical Application Circuit
Long Period Delay Generator
Trigger
Output
Reset
18
27
36
45
VDD
RA
RB
Operating conditions:
RA = RB = 4.7MΩ,
Internal counter = 106 (maximum)
CINT = 100pF, Delay = 16.3 minutes
Average power = 7.5 µW at VDD = 3.0V
Figure 2
Ordering Information
Part Number Package Description
CSS555C-ID
8 pin plastic DIP
CSS555C-IS
8 pin plastic SOIC
See page 9 for more details and options.
Custom Silicon Solutions Inc.
17951 Sky Park Circle, Suite F
Irvine, CA 92614
(949) 797-9220 • FAX: (949) 797-9225 • www.CustomSiliconSolutions.com
Custom Silicon Solutions, Inc. ©2009
1
Version 1.1, May 2009
1 page  
CSS555C
Micropower Timer (with Internal Timing Capacitor)
Pin Descriptions
Pin Number
Pin Name
Primary Function (Normal Mode)
Secondary Function (EE Programming)
1 VSS
Ground
2
TRIGGER
Initiates timing cycles (Active low)
Serial Clock
3
OUTPUT
Timer Output (CMOS Levels)
Serial Data Out
4
RESET
Asynchronous timer reset (Active low)
Serial Data In
5
CONTROL V
Upper comparator switch level
R/W enable (Active if VCTRL < 0.5V)
6
THRESHOLD
Upper comparator analog input
7 DISCHARGE Open drain FET, on when OUTPUT = 1
8 VDD
Positive voltage supply
Table 4
Applications Information
General
The CSS555C IC may be used in many applications as a
direct replacement for the popular 555 timer. It features
the lowest 555 operating current and a minimum supply
voltage of 1.2V. It also features a programmable decade
counter for generating long time delays. An internal
EEPROM stores the counter configuration: Divide by 1
(standard 555) or divide by 10, 100, 103, 104, 105 or 106.
The internal counter allows long time delays to be
generated with small value capacitors.
Delay Time Equations:
For standard supply voltages (VLOW Bit = 0)
Charge time (VTH = 0V to ⅔ VDD) = 1.1 x RA x CTotal
For low voltage mode (VLOW Bit = 1)
Charge time (VTH = 0V to 0.9 VDD) = 2.3 x RA x CTotal
where CTotal = (CInternal + CExternal) or (CTI + CT)
RESET
TRIGGER
Monostable Operation
(Standard 555 Mode)
The circuit in Figure 6 shows a monostable or “one shot”
configuration. A single, positive output pulse is generated
on the falling edge of the TRIGGER input. When
TRIGGER goes low, a flip-flop is set, the OUTPUT pin is
set high and DISCHARGE allows the timing capacitor to
charge towards VDD via RA. When VTH reaches the upper
comparator trip level, the flip-flop is reset, OUTPUT is
forced low and DISCHARGE pulls VTH to GND. After VTH
has discharged, the circuit is ready for the next trigger
pulse. Typical signal waveforms are shown in Figure 7.
The RESET input must be held high (inactive) during the
timing cycle. If RESET is brought low, the OUTPUT pin is
immediately forced low and the cycle is terminated.
Trigger
Output
Reset
Trigger
Output
Reset
CSS555C
VSS
VDD
VDD
RA
Trigger Dischg
Output Thresh VTH
Reset Control
CT
Optional
OUTPUT
Mult = 1
VCAP
⅔ VDD
0V
Figure 7 – Monostable Waveforms (Std. Mode)
Figure 8 provides a log-log selection chart. It shows the
time delay for various combinations of RA and CTotal. With
the counter bypassed (Mult = 1), time delays from 1usec to
1 second are easily generated with capacitor values from
100pF to 1uF. For long time delays (or medium delay
times using small capacitor values) the “Extended Period”
configuration should be used. (See the next section.)
1.0000
0.1000
Blue:
Std. VDD
RA = 1K
10K 100K
1M
10M
0.0100
Figure 6 – Monostable Circuit (Std. Mode)
0.0010
In the monostable configuration, the duration of the timing
cycle is simply the time required to charge the timing
capacitor from GND to the upper comparator trip level. The
trip level is nominally ⅔ VDD. At low supply voltages it is
increased to 0.9 VDD. (An EEPROM bit controls this
selection.) The delay time equations for both conditions
are provided in the following paragraph.
0.0001
0.01
Green:
Low VDD
0.10
1.00
10.00
100.00
Delay Time (ms)
Figure 8 – Time Delay Chart
1000.00
Custom Silicon Solutions, Inc. ©2009
5
Version 1.1, May 2009
5 Page 
CSS555C
Micropower Timer (with Internal Timing Capacitor)
Typical Performance Characteristics (continued)
Minimum Trigger Pulse Width vs. Trigger
Level
5.0
Standard Trip Levels (1/3 & 2/3 VDD)
4.5
4.0
3.5
3.0
2.5
2.0 Power Setting
Micro
Low
1.5
VDD
5.0V
3.0V
2.0V
1.0
0.5
0.0
0 5 10 15 20 25
Trigger Low Level (%VDD)
30
Minimum Trigger Pulse Width vs. Trigger
Level
5.0
Low VDD Trip Levels (10% & 90% VDD)
4.5
4.0
3.5
3.0 Power Setting
Micro
Low
2.5
VDD
3.0V
2.0V
1.5V
2.0
1.5
1.0
0.5
0.0
35 0 1 2 3 4 5 6 7 8 9 10
Trigger Low Level (%VDD)
Figure 27 Trigger Pulse Width (Std. VDD)
Figure 28 Trigger Pulse Width (Low VDD)
2.0
1.5
1.0
0.5
0.0
0.1
2.0
1.5
1.0
0.5
0.0
0.1
Timer OUTPUT High Voltage vs. Source
Current
VDD
3.0V
VDD
5.0V
VDD
1.5V
1.0 10.0
Output Source Current
(mA)
Figure 29 OUTPUT VOH vs. IOH
100.0
Timer OUTPUT Drive High vs. Temperature
10
VDD = 5.0V
9
IOH measured at VOH = VDD - 0.2V
8
7
VDD = 3.0V
6
5
4
3
VDD = 1.5V
2
1
0
-50
-25
0 25 50 75
Temperature (degrees C)
100 125
Figure 30 OUTPUT IOH vs. Temperature
Timer OUTPUT Low Voltage vs. Sink Current
VDD
1.5V
VDD
3.0V
VDD
5.0V
Timer OUTPUT Drive Low vs. Temperature
10
9
VDD = 5.0V
8
IOL measured at VOL = 0.2V
7
VDD = 3.0V
6
5
4
VDD = 1.5V
3
2
1
1.0 10.0
Output Sink Current (mA)
100.0
0
-50
-25
0 25 50 75
Temperature (degrees C)
100 125
Figure 31 OUTPUT VOL vs. IOL
Figure 32 OUTPUT IOL vs. Temperature
Custom Silicon Solutions, Inc. ©2009
11
Version 1.1, May 2009
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet CSS555C.PDF ] | |
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