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PDF AR9287 Data sheet ( Hoja de datos )
| Número de pieza | AR9287 | |
| Descripción | Single-Chip 2x2 MIMO MAC/BB/Radio | |
| Fabricantes | Atheros | |
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Data Sheet
February 2010
AR9287 Single-Chip 2x2 MIMO MAC/BB/Radio with PCIE
Interface for 802.11n 2.4 GHz WLANs
General Description
The Atheros AR9287 is a highly integrated
single-chip solution for 2.4 GHz 802.11n-ready
WLANs to enable high-performance 2x2 MIMO
configurations for applications demanding
robust link quality and maximum throughput
and range. The AR9287 integrates a multi-
protocol MAC, baseband processor, analog-to-
digital and digital-to-analog (ADC/DAC)
converters, 2x2 MIMO radio transceiver
including LNA, PA, and RF switch, and PCI
Express interface in an all-CMOS device for low
power and small form factor applications.
The AR9287 implements half-duplex OFDM,
CCK, and DSSS baseband processing, supporting
up to 150 Mbps for 20 MHz and 300 Mbps for
40 MHz channel operations respectively, and
IEEE 802.11b/g data rates. Additional features
include signal detection, automatic gain control,
frequency offset estimation, symbol timing, and
channel estimation. The AR9287 MAC supports
the 802.11 wireless MAC protocol, 802.11i
security, receive and transmit filtering, error
recovery, and quality of service (QoS).
The AR9287 supports two simultaneous traffic
streams using up to two integrated transmit
chains and receive chains for high throughput
and range performance. Transmit chains combine
baseband in-phase (I) and quadrature (Q) signals,
convert them to the desired frequency, and drive
the RF signal to multiple antennas. Receive
chains convert RF signal to baseband I and Q
outputs. The frequency synthesizer supports
one-MHz steps to match frequencies defined by
IEEE 802.11b/g/n specifications.
The AR9287 supports frame data transfer to and
from the host using a PCIE interface providing
interrupt generation and reporting, power save,
and status reporting. Other external interfaces
include serial EEPROM and GPIOs. The AR9287
operates with standard legacy 802.11b/g devices.
Features
■ All-CMOS MIMO solution interoperable with
IEEE 802.11b/g/n WLANs
■ 2x2 MIMO technology improves effective
throughput and range over existing
802.11b/g products
■ Integrated LNAs, PAs, and RF switches
eliminate the need for external front-end
modules
■ Supports spatial multiplexing, cyclic-delay
diversity (CDD), and maximal ratio
combining (MRC)
■ 2.4 GHz WLAN MAC/BB processing
■ BPSK, QPSK, 16 QAM, 64 QAM, DBPSK,
DQPSK, and CCK modulation schemes
■ Data rates of up to 150 Mbps for 20 MHz
channels and 300 Mbps for 40 MHz channels
■ Wireless multimedia enhancements for QoS
■ 802.11e-compatible bursting
■ Support for IEEE 802.11e, h, and i standards
■ WEP, TKIP, and AES hardware encryption
■ 20 and 40 MHz channelization
■ PCIE 1.1 compliant
■ Support for 2–3 wire Bluetooth coexistence
■ Reduced (short) guard interval
■ Frame aggregation
■ Block ACK
■ IEEE 1149.1 standard test access port and
boundary scan architecture supported
■ 9 mm x 9 mm 76-pin LPCC package
AR9287 System Block Diagram
© 2009-2010 by Atheros Communications, Inc. All rights reserved. Atheros®, Atheros Driven®, Align®, Atheros XR®, Driving the Wireless Future®, Intellon®, No New Wires®,
Orion® , PLC4Trucks®, Powerpacket®, Spread Spectrum Carrier®, SSC®, ROCm®, Super A/G®, Super G®, Super N®, The Air is Cleaner at 5-GHz®, Total 802.11®, U-Nav®,
Wake on Wireless®, Wireless Future. Unleashed Now.®, and XSPAN®, are registered by Atheros Communications, Inc. Atheros SST™, Signal-Sustain Technology™, Ethos™,
Install N Go™, IQUE™, ROCm™, amp™, Simpli-Fi™, There is Here™, U-Map™, U-Tag™, and 5-UP™ are trademarks of Atheros Communications, Inc. The Atheros logo is a
registered trademark of Atheros Communications, Inc. All other trademarks are the property of their respective holders. Subject to change without notice.
COMPANY CONFIDENTIAL
•1
1 page  
1. Pin Descriptions
This section contains a package pinout (see
Figure 1-1 and Table 1-1) and a tabular listing
of the signal descriptions.
This nomenclature is used for signal names:
NC No connection should be made to
this pin
_L At the end of the signal name,
indicates active low signals
P At the end of the signal name,
indicates the positive side of a
differential signal
N At the end of the signal name
indicates the negative side of a
differential signal
This nomenclature is used for signal types:
I Digital input signal
I/O A digital bidirectional signal
IA Analog input signal
IH Input signals with weak internal
pull-up, to prevent signals from
floating when left open
IL Input signals with weak internal
pull-down, to prevent signals
from floating when left open
O A digital output signal
OA An analog output signal
OD A digital output signal with open
drain
P A power or ground signal
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
AR9287 Single-Chip 2x2 MIMO MAC/BB/Radio for 802.11n WLANs • 1
February 2010 • 1
5 Page 
2. Functional Description
2.1 Overview
The AR9287 consists of four major functional
blocks: PCI Express interface, MAC, digital
PHY, and radio.
The IEEE 802.11 MAC functionality is
partitioned between the host and the AR9287.
IEEE 802.11 MAC data service is provided by
the MAC of the AR9287, while the host
software, with the aid of the AR9287 MAC,
controls Tx and Rx queue processing.
The baseband digital processing functions are
implemented by the digital PHY of the
AR9287. The radio frequency (RF) and
baseband analog processing are provided by
the integrated radio. The physical layer (PHY)
is partitioned between the baseband processor
and the radio. The configuration block, PLL,
ADC, DAC, EEPROM interface, JTAG, antenna
control, and GPIO complete the AR9287
functionality. See Figure 2-1.
Figure 2-1. Functional Block Diagram of the AR9287
2.1.1 Configuration Block
The configuration block provides control,
status, and configuration, for each major
functional block. This block contains registers
accessed by other blocks and by the host using
the PCI Express interface.
Table 2-1. Offset Addresses
Offset Location
0x0000–0x07FC
0x0800–0x0FFC
0x1000–0x1FFC
0x2000–0x3FFC
Usage
MAC DMA general
MAC DMA QCU registers
DCU registers
EEPROM access register
0x4000–0x4FFC
0x8000–0x98FC
Host interface
PCU registers
2.1.2 AR9287 Address MAP
Internal registers of the various functional
blocks and the AR9287 peripheral interface are
accessible with the host using the PCI Express
interface. These register locations are defined
as offset addresses. The combination of the host
base address and the offset address allows
access to a particular internal register. Table 2-1
lists the offset addresses for the AR9287
internal registers and peripheral interface.
Description
DMA access
Control and status register for QCU
Control and status register for DCU
Memory location of EEPROM are mapped to this
address range and allow access to EEPROM
Control and status register for host interface
Control and status register for PCU
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
AR9287 Single-Chip 2x2 MIMO MAC/BB/Radio for 802.11n WLANs • 7
February 2010 • 7
11 Page | ||
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| PDF Descargar | [ Datasheet AR9287.PDF ] | |
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