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PDF ST10F273E Data sheet ( Hoja de datos )
| Número de pieza | ST10F273E | |
| Descripción | 16-bit MCU | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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ST10F273E
16-bit MCU with 512 Kbyte Flash memory and 36 Kbyte RAM
Feature summary
■ High performance 16-bit CPU with DSP
functions
– 31.25ns instruction cycle time at 64 MHz
max CPU clock
– Multiply/accumulate unit (MAC) 16 x 16-bit
multiplication, 40-bit accumulator
– Enhanced boolean bit manipulations
– Single-cycle context switching support
■ Memory organization
– 512 Kbyte on-chip Flash memory single
voltage with erase/program controller (full
performance, 32-bit fetch)
– 100K erasing/programming cycles.
– Up to 16 Mbyte linear address space for
code and data (5 Mbytes with CAN or I2C)
– 2 Kbyte on-chip internal RAM (IRAM)
– 34 Kbyte on-chip extension RAM (XRAM)
– Programmable external bus configuration &
characteristics for different address ranges
– 5 programmable chip-select signals
– Hold-acknowledge bus arbitration support
■ Interrupt
– 8-channel peripheral event controller for
single cycle interrupt driven data transfer
– 16-priority-level interrupt system with 56
sources, sampling rate down to 15.6ns
■ Timers
– 2 multifunctional general purpose timer
units with 5 timers
■ Two 16-channel capture / compare units
■ 4-channel PWM unit + 4-channel XPWM
PQFP144 (28 x 28 x 3.4mm) TQFP144 (20 x 20 x 1.4mm)
(Plastic Quad Flat Package)
(Thin Quad Flat Package)
■ A/D Converter
– 24-channel 10-bit
– 3µs Minimum conversion time
■ Serial channels
– 2 synch. / asynch. serial channels
– 2 high-speed synchronous channels
– I2C standard interface
■ 2 CAN 2.0B interfaces operating on 1 or 2 CAN
busses (64 or 2x32 messages, C-CAN version)
■ Fail-safe protection
– Programmable watchdog timer
– Oscillator watchdog
■ On-chip bootstrap loader
■ Clock generation
– On-chip PLL and 4 to 12 MHz oscillator
– Direct or prescaled clock input
■ Real time clock and 32 kHz on-chip oscillator
■ Up to 111 general purpose I/O lines
– Individually programmable as input, output
or special function
– Programmable threshold (hysteresis)
■ Idle, power down and stand-by modes
■ Single voltage supply: 5 V ±10%.
Order codes
Part number
F273-CEG-P
F273-CEG-P-TR
F273-CEG-T
F273-CEG-T-TR
Package
PQFP144
TQFP144
Packing
Tray
Tape & Reel
Tray
Tape & Reel
Temperature
range(°C)
-40 to +125
-40 to +125
-40 to +105
CPU frequency
range (MHz)
1 to 64
1 to 40
1 to 48
May 2006
Rev 1
1/179
www.st.com
1
1 page  
ST10F273E
Contents
21.3
21.2.1 Protected power down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
21.2.2 Interruptible power down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
21.3.1 Entering stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
21.3.2 Exiting stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
21.3.3 Real time clock and stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
21.3.4 Power reduction modes summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
22 Programmable output clock divider . . . . . . . . . . . . . . . . . . . . . . . . . . 110
23 Register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
23.1 Special function registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
23.2 X-registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
23.3 Flash registers ordered by name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
23.4 Identification registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
24 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
24.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
24.2 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
24.3 Power considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
24.4 Parameter interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
24.5 DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
24.6 Flash characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
24.7 A/D converter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
24.7.1 Conversion timing control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
24.7.2 A/D conversion accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
24.7.3 Total unadjusted error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
24.7.4 Analog reference pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
24.8 AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
24.8.1 Test waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
24.8.2 Definition of internal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
24.8.3 Clock generation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
24.8.4 Prescaler operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
24.8.5 Direct drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
24.8.6 Oscillator watchdog (OWD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
24.8.7 Phase locked loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
5/179
5 Page 
ST10F273E
1 Introduction
Introduction
The ST10F273E device is a derivative of the STMicroelectronics ST10 family of 16-bit
single-chip CMOS microcontrollers.
The ST10F273E combines high CPU performance (up to 32 million instructions per second)
with high peripheral functionality and enhanced I/O-capabilities. It also provides on-chip
high-speed single voltage Flash memory, on-chip high-speed RAM, and clock generation
via PLL.
ST10F273E is processed in 0.18mm CMOS technology. The MCU core and the logic is
supplied with a 5 V to 1.8 V on-chip voltage regulator. The part is supplied with a single 5 V
supply and I/Os work at 5 V.
The device is upward compatible with the ST10F269 device, with the following set of
differences:
Flash control interface is now based on STMicroelectronics third generation of stand-alone
Flash memories (M29F400 series), with an embedded Program/Erase Controller. This
completely frees up the CPU during programming or erasing the Flash.
Only one supply pin (ex DC1 in ST10F269, renamed into V18) on the QFP144 package is
used for decoupling the internally generated 1.8V core logic supply. Do not connect this pin
to 5.0 V external supply. Instead, this pin should be connected to a decoupling capacitor
(ceramic type, typical value 10nF, maximum value 100nF).
The AC and DC parameters are modified due to a difference in the maximum CPU
frequency.
A new VDD pin replaces DC2 of ST10F269.
EA pin assumes a new alternate functionality: it is also used to provide a dedicated power
supply (see VSTBY) to maintain biased a portion of the XRAM (16 Kbytes) when the main
Power Supply of the device (VDD and consequently the internally generated V18) is turned
off for low power mode, allowing data retention. VSTBY voltage shall be in the range 4.5 to
5.5 volts and a dedicated embedded low power voltage regulator is in charge to provide the
1.8 V for the RAM, the low-voltage section of the 32 kHz oscillator and the Real Time Clock
module when not disabled. It is allowed to exceed the upper limit up to 6 V for a very short
period of time during the global life of the device and exceed the lower limit down to 4 V
when RTC and 32 kHz on-chip oscillator are not used.
A second SSC mapped on the XBUS is added (SSC of ST10F269 becomes here SSC0,
while the new one is referred as XSSC or simply SSC1). Note that some restrictions and
functional differences due to the XBUS peculiarities are present between the classic SSC
and the new XSSC.
A second ASC mapped on the XBUS is added (ASC0 of ST10F269 remains ASC0, while
the new one is referred as XASC or simply as ASC1). Note that some restrictions and
functional differences due to the XBUS peculiarities are present between the classic ASC
and the new XASC.
A second PWM mapped on the XBUS is added (PWM of ST10F269 becomes here PWM0,
while the new one is referred as XPWM or simply as PWM1). Note that some restrictions
and functional differences due to the XBUS peculiarities are present between the classic
PWM and the new XPWM.
An I2C interface on the XBUS is added (see X-I2C or simply I2C interface).
11/179
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ST10F273E.PDF ] | |
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