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PDF ST10F276E Data sheet ( Hoja de datos )
| Número de pieza | ST10F276E | |
| Descripción | 16-bit MCU | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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ST10F276E
16-bit MCU with MAC unit
832 Kbyte Flash memory and 68 Kbyte RAM
Datasheet − production data
Features
■ Highly performance 16-bit CPU with DSP
functions
– 31.25ns instruction cycle time at 64MHz
max CPU clock
– Multiply/accumulate unit (MAC) 16 x 16-bit
multiplication, 40-bit accumulator
– Enhanced boolean bit manipulations
– Single-cycle context switching support
■ On-chip memories
– 512 Kbyte Flash memory (32-bit fetch)
– 320 Kbyte extension Flash memory (16-bit
fetch)
– Single voltage Flash memories with
erase/program controller and 100K
erasing/programming cycles
– Up to 16 Mbyte linear address space for
code and data (5 Mbytes with CAN or I2C)
– 2 Kbyte internal RAM (IRAM)
– 66 Kbyte extension RAM (XRAM)
■ External bus
– Programmable external bus configuration &
characteristics for different address ranges
– 5 programmable chip-select signals
– Hold-acknowledge bus arbitration support
■ Interrupt
– 8-channel peripheral event controller for
single cycle interrupt driven data transfer
– 16-priority-level interrupt system with 56
sources, sampling rate down to 15.6ns
■ Timers
– 2 multi-functional general purpose timer
units with 5 timers
■ Two 16-channel capture / compare units
PQFP144 (28 x 28 x 3.4mm)
(Plastic quad flat package)
LQFP144 (20 x 20 x 1.4mm)
(Low profile plastic quad
flat package)
■ 4-channel PWM unit + 4-channel XPWM
■ A/D converter
– 24-channel 10-bit
– 3 µs minimum conversion time
■ Serial channels
– 2 synch. / asynch. serial channels
– 2 high-speed synchronous channels
– 1 I2C standard interface
■ 2 CAN 2.0B interfaces operating on 1 or 2 CAN
busses (64 or 2x32 message, C-CAN version)
■ Fail-safe protection
– Programmable watchdog timer
– Oscillator watchdog
■ On-chip bootstrap loader
■ Clock generation
– On-chip PLL with 4 to 12 MHz oscillator
– Direct or prescaled clock input
■ Real-time clock and 32 kHz on-chip oscillator
■ Up to 111 general purpose I/O lines
– Individually programmable as input, output
or special function
– Programmable threshold (hysteresis)
■ Idle, power down and stand-by modes
■ Single voltage supply: 5V ±10% (embedded
regulator for 1.8 V core supply)
September 2013
This is information on a product in full production.
Doc ID 12303 Rev 4
1/235
www.st.com
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1 page  
ST10F276E
Contents
12.3
12.2.1 Open drain mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
12.2.2 Input threshold control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Alternate port functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
13 A/D converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
14 Serial channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
14.1 Asynchronous / synchronous serial interfaces . . . . . . . . . . . . . . . . . . . . . 95
14.2 ASCx in asynchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
14.3 ASCx in synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
14.4 High speed synchronous serial interfaces . . . . . . . . . . . . . . . . . . . . . . . . 97
15 I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
16 CAN modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
16.1 Configuration support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
16.2 CAN bus configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
17 Real-time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
18 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
19 System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
19.1 Input filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
19.2 Asynchronous reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
19.3 Synchronous reset (warm reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
19.4 Software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
19.5 Watchdog timer reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
19.6 Bidirectional reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
19.7 Reset circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
19.8 Reset application examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
19.9 Reset summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
20 Power reduction modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
20.1 Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
20.2 Power down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
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ST10F276E
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
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Figure 8.
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Figure 10.
Figure 11.
Figure 12.
Figure 13.
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Figure 38.
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Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
Figure 48.
Logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Pin configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Flash modules structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
ST10F276E new standard bootstrap loader program flow . . . . . . . . . . . . . . . . . . . . . . . . . 49
Booting steps for ST10F276E. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Hardware provisions to activate the BSL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Memory configuration after reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
UART bootstrap loader sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Baud rate deviation between host and ST10F276E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
CAN bootstrap loader sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Bit rate measurement over a predefined zero-frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Reset boot sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
CPU Block Diagram (MAC Unit not included). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
MAC unit architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
X-Interrupt basic structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Block diagram of GPT1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Block diagram of GPT2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Block diagram of PWM module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Connection to single CAN bus via separate CAN transceivers . . . . . . . . . . . . . . . . . . . . 101
Connection to single CAN bus via common CAN transceivers. . . . . . . . . . . . . . . . . . . . . 102
Connection to two different CAN buses (e.g. for gateway application). . . . . . . . . . . . . . . 103
Connection to one CAN bus with internal Parallel Mode enabled . . . . . . . . . . . . . . . . . . 103
Asynchronous power-on RESET (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Asynchronous power-on RESET (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Asynchronous hardware RESET (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Asynchronous hardware RESET (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Synchronous short / long hardware RESET (EA = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Synchronous short / long hardware RESET (EA = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Synchronous long hardware RESET (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Synchronous long hardware RESET (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
SW / WDT unidirectional RESET (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
SW / WDT unidirectional RESET (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
SW / WDT bidirectional RESET (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
SW / WDT bidirectional RESET (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
SW / WDT bidirectional RESET (EA = 0) followed by a HW RESET . . . . . . . . . . . . . . . . 123
Minimum external reset circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
System reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Internal (simplified) reset circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Example of software or watchdog bidirectional reset (EA = 1) . . . . . . . . . . . . . . . . . . . . . 126
Example of software or watchdog bidirectional reset (EA = 0) . . . . . . . . . . . . . . . . . . . . . 127
PORT0 bits latched into the different registers after reset . . . . . . . . . . . . . . . . . . . . . . . . 130
External RC circuitry on RPD pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Port2 test mode structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Supply current versus the operating frequency (RUN and IDLE modes) . . . . . . . . . . . . . 184
A/D conversion characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
A/D converter input pins scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Charge sharing timing diagram during sampling phase . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Doc ID 12303 Rev 4
11/235
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ST10F276E.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| ST10F276 | (ST10F273 / ST10F276) 16-bit MCU with MAC unit / up to 832 Kbytes Flash memory and up to 68 Kbytes RAM |  ST Microelectronics |
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