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CED30P10 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 CED30P10
기능 P-Channel Enhancement Mode Field Effect Transistor
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CED30P10 데이터시트, 핀배열, 회로
CED30P10/CEU30P10
P-Channel Enhancement Mode Field Effect Transistor
FEATURES
-100V, -30A, RDS(ON) = 76m@VGS = -10V.
RDS(ON) = 92m@VGS = -4.5V.
Super high dense cell design for extremely low RDS(ON).
High power and current handing capability.
Lead free product is acquired.
TO-251 & TO-252 package.
D
D
G
S
CEU SERIES
TO-252(D-PAK)
G
DS
CED SERIES
TO-251(I-PAK)
G
S
ABSOLUTE MAXIMUM RATINGS Tc = 25 C unless otherwise noted
Parameter
Symbol
Limit
Drain-Source Voltage
Gate-Source Voltage
Drain Current-Continuous
Drain Current-Pulsed a
Maximum Power Dissipation @ TC = 25 C
- Derate above 25 C
VDS
VGS
ID
IDM
PD
-100
±20
-30
-120
150
1.2
Operating and Store Temperature Range
TJ,Tstg
-55 to 150
Thermal Characteristics
Parameter
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient
Symbol
RθJC
RθJA
Limit
1
50
Units
V
V
A
A
W
W/ C
C
Units
C/W
C/W
2009.Nov
http://www.cet-mos.com
1




CED30P10 pdf, 반도체, 판매, 대치품
CED30P10/CEU30P10
10 VDS=-80V
ID=-11A
8
6
4
2
0
0 20 40 60 80
Qg, Total Gate Charge (nC)
Figure 7. Gate Charge
VDD
VIN RL
D VOUT
VGS
RGEN G
S
103
RDS(ON)Limit
102
100ms
1ms
10ms
101 DC
TC=25 C
TJ=175 C
100 Single Pulse
100 101 102 103
-VDS, Drain-Source Voltage (V)
Figure 8. Maximum Safe
Operating Area
td(on)
VOUT
t on
tr
td(off)
90%
10% INVERTED
toff
tf
90%
10%
VIN
10%
50%
90%
50%
PULSE WIDTH
Figure 9. Switching Test Circuit
Figure 10. Switching Waveforms
100
D=0.5
0.2
10-1
0.1
0.05
10-2
10-4
0.02
0.01
Single Pulse
10-3
10-2
10-1
100
Square Wave Pulse Duration (sec)
PDM
t1
t2
1. R JC (t)=r (t) * R JC
2. R JC=See Datasheet
3. TJM-TC = P* R JC (t)
4. Duty Cycle, D=t1/t2
101
102
Figure 11. Normalized Thermal Transient Impedance Curve
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