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PDF PHB63NQ03LT Data sheet ( Hoja de datos )
| Número de pieza | PHB63NQ03LT | |
| Descripción | logic level FET | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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PHP/PHB/PHD63NQ03LT
TrenchMOS™ logic level FET
Rev. 01 — 14 June 2002
Product data
1. Product profile
1.1 Description
N-channel enhancement mode field-effect transistor in a plastic package using
TrenchMOS™ technology.
Product availability:
PHP63NQ03LT in SOT78 (TO-220AB)
PHB63NQ03LT in SOT404 (D2-PAK)
PHD63NQ03LT in SOT428 (D-PAK).
1.2 Features
s Logic level compatible
s Low gate charge
1.3 Applications
s DC to DC converters
s Switched mode power supplies
1.4 Quick reference data
s VDS = 30 V
s Ptot = 111 W
s ID = 68.9 A
s RDSon ≤ 13 mΩ
2. Pinning information
Table 1: Pinning - SOT78, SOT404, SOT428 simplified outline and symbol
Pin Description
Simplified outline
1 gate (g)
2 drain (d)
[1] mb
mb
mb
3 source (s)
mb mounting base,
connected to drain (d)
2
1 3 MBK116
2
1
Top view
3
MBK091
Symbol
g
MBB076
d
s
MBK106
123
SOT78 (TO-220)
SOT404 (D2-PAK)
[1] It is not possible to make connection to pin 2 of the SOT404 or SOT428 packages.
SOT428 (D-PAK)
1 page  
Philips Semiconductors
PHP/PHB/PHD63NQ03LT
TrenchMOS™ logic level FET
5. Characteristics
Table 4: Characteristics
Tj = 25 °C unless otherwise specified
Symbol Parameter
Conditions
Static characteristics
V(BR)DSS drain-source breakdown voltage
VGS(th) gate-source threshold voltage
IDSS drain-source leakage current
IGSS
RDSon
gate-source leakage current
drain-source on-state resistance
Dynamic characteristics
ID = 250 µA; VGS = 0 V
Tj = 25 °C
Tj = −55 °C
ID = 1 mA; VDS = VGS; Figure 9
Tj = 25 °C
Tj = 175 °C
Tj = −55 °C
VDS = 30 V; VGS = 0 V
Tj = 25 °C
Tj = 175 °C
VGS = ±20 V; VDS = 0 V
VGS = 5 V; ID = 25 A; Figure 7 and 8
Tj = 25 °C
Tj = 175 °C
VGS = 10 V; ID = 25 A; Figure 7 and 8
Qg(tot) total gate charge
Qgs gate-source charge
Qgd gate-drain (Miller) charge
Ciss input capacitance
Coss output capacitance
Crss reverse transfer capacitance
td(on)
turn-on delay time
tr rise time
td(off)
turn-off delay time
tf fall time
Source-drain diode
ID = 50 A; VDD = 15 V; VGS = 5 V; Figure 13
VGS = 0 V; VDS = 25 V; f = 1 MHz; Figure 11
VDD = 15 V; ID = 25 A; VGS = 4.5 V; RG = 5.6 Ω
VSD source-drain (diode forward) voltage IS = 25 A; VGS = 0 V; Figure 12
trr reverse recovery time
IS = 10 A; dIS/dt = −100 A/µs; VGS = 0 V
Qr recovered charge
Min Typ Max Unit
30 - - V
27 - - V
V
1 1.9 2.5 V
0.6 - - V
- - 2.9 V
- 0.05 1 µA
- - 500 µA
- 10 100 nA
- 15 17.7 mΩ
- 24 28.3 mΩ
- 11 13 mΩ
- 9.6 - nC
- 4 - nC
- 3.2 - nC
- 920 - pF
- 275 - pF
- 110 - pF
- 12 - ns
- 140 - ns
- 10.5 - ns
- 14 - ns
- 0.95 1.2 V
- 23 - ns
- 12 - nC
9397 750 09822
Product data
Rev. 01 — 14 June 2002
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
5 of 14
5 Page 
Philips Semiconductors
PHP/PHB/PHD63NQ03LT
TrenchMOS™ logic level FET
Plastic single-ended surface mounted package (Philips version of D-PAK); 3 leads
(one lead cropped)
SOT428
seating plane
y
A
EA
A2
b2 A1
mounting
base
D
HE
L2
2
1
L
3
b1
e
b wM A
e1
L1
c
D1
E1
0 10 20 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT A A1(1) A2 b
b1 b2
c
mm 2.38 0.65 0.93 0.89 1.1 5.46 0.4
2.22 0.45 0.73 0.71 0.9 5.26 0.2
D
6.22
5.98
D1 E
min.
4.0 6.73
6.47
E1 e e1 HE L
4.81 2.285 4.57 10.4 2.95
4.45 9.6 2.55
L1
min.
0.5
L2
0.9
0.5
Note
1. Measured from heatsink back to lead.
OUTLINE
VERSION
IEC
REFERENCES
JEDEC
JEITA
EUROPEAN
PROJECTION
SOT428
TO-252
SC-63
w
y
max.
0.2 0.2
ISSUE DATE
99-09-13
01-12-11
Fig 16. SOT428 (D-PAK)
9397 750 09822
Product data
Rev. 01 — 14 June 2002
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
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