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PDF LTC4282 Data sheet ( Hoja de datos )
| Número de pieza | LTC4282 | |
| Descripción | High Current Hot Swap Controller | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de LTC4282 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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LTC4282
High Current Hot Swap
Controller with I2C Compatible Monitoring
Features
nn Allows Safe Board Insertion Into Live Backplane
nn 12-/16-Bit ADC with ±0.7% Total Unadjusted Error
nn Monitors Current, Voltage, Power and Energy
nn Controls Two Parallel N-Channel MOSFETs for High
Current Applications
nn Internal EEPROM for Nonvolatile Configuration
nn Wide Operating Voltage Range: 2.9V to 33V
nn I2C/SMBus Digital Interface (Coexists with PMBus
Devices)
nn 12V Gate Drive for Lower MOSFET RDS(ON)
nn Programmable Current Limit with 2% Accuracy
nn MOSFET Power Limiting with Current Foldback
nn Continuously Monitors MOSFET Health
nn Stores Minimum and Maximum Measurements
nn Alerts When Alarm Thresholds Exceeded
nn Input Overvoltage/Undervoltage Protection
nn Three General Purpose Input/Outputs
nn Internal ±5% or External Timebases
nn 32-Pin 5mm × 5mm QFN Package
Applications
nn Enterprise Servers and Data Storage Systems
nn Network Routers and Switches
nn Base Stations
nn Platform Management
Description
The LTC®4282 Hot Swap™ controller allows a board to
be safely inserted and removed from a live backplane.
Using one or more external N-channel pass transistors,
board supply voltage and inrush current are ramped up
at an adjustable rate. An I2C interface and onboard ADC
allows for monitoring of board current, voltage, power,
energy and fault status.
The device features analog foldback current limiting and
supply monitoring for applications from 2.9V to 33V.
Dual 12V gate drive allows high power applications to
either share safe operating area across parallel MOSFETs
or support a 2-stage start-up that first charges the load
capacitance followed by enabling a low on-resistance
path to the load.
The LTC4282 is well suited to high power applications
because the precise monitoring capability and accurate
current limiting reduce the extremes in which both loads
and power supplies must safely operate. Non-volatile
configuration allows for flexibility in the autonomous
generation of alerts and response to faults.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and Hot
Swap is a trademark of Linear Technology Corporation. All other trademarks are the property of
their respective owners. Patents pending.
Typical Application
12V, 100A Plug-In Board Application
0.25mΩ
VOUT
12V
0.25mΩ
10Ω
+
12V
100A
SDA
SCL
ALERT
12V
GND
BACKPLANE PLUG-IN
BOARD
SMCJ15CA
×2
1Ω 1Ω
1Ω 1Ω
10Ω
NC
NC
NC
100k
VDD SENSE2+ ADC+ SENSE1+ SENSE1– ADC– SENSE2– GATE1 GATE2
UV
OV
SDAI
SDAO
SCL
ALERT
ADR0
ADR1
ADR2
ON
INTVCC
LTC4282
SOURCE
FB
GPIO1
TIMER
GPIO2
GPIO3
WP CLKIN CLKOUT GND
4.7µF
10nF
4282 TA01
NC
NC
POWER
GOOD
GP
GP
Start-Up Waveforms
VDD
10V/DIV
CONTACT BOUNCE
∆VGATE
10V/DIV
VSOURCE
10V/DIV
GPIO1(PG)
10V/DIV
50ms DE-BOUNCE
20ms/DIV
For more information www.linear.com/LTC4282
4282 TA01b
4282f
1
1 page  
LTC4282
E lectrical Characteristics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDD = 12V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN TYP MAX
ISDA,SCL(OH)
VSDAO(OL)
ISDAO(OH)
I2C Interface Timing
SDAI, SCL Input Current
SDAO Output Low Voltage
SDAO Pin Input Leakage Current
SCL, SDA = 5V
I = 3mA
VSDAO = 33V
l ±1
l 0.3 0.4
l 0 ±1
fSCL(MAX)
tBUF(MIN)
Maximum SCL Clock Frequency
Bus Free Time Between START and STOP
Conditions
l 400
l
1000
0.12
1.3
tHD,STA(MIN)
Hold Time After (Repeated) START Condition
tSU,STA(MIN)
Repeated START Condition Set-Up Time
tSU,STO(MIN)
STOP Condition Set-Up Time
tHD,DATI(MIN)
Data Hold Time (Input)
tHD,DATO
Data Hold Time (Output)
tSU,DAT(MIN)
Data Set-Up Time
tSP(MAX)
Suppressed Spike Pulse Width Maximum
CX SCL, SDA Input Capacitance
tD-STUCK
I2C Stuck Bus Timeout
EEPROM Characteristics
(Note 4)
l 30 600
l 30 600
l 140 600
l 30 100
l 300 500 900
l 30 600
l 50 110 250
l 10
l 25 30 35
Endurance
1 Cycle = 1 Write (Notes 7, 8)
l 10,000
Retention
(Notes 7, 8)
l 20
tWRITE
Write Operation Time
l 1 2.2 4
UNITS
µA
V
µA
kHz
µs
µs
ns
ns
ns
ns
ns
ns
pF
ms
Cycles
Years
ms
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into pins are positive. All voltages are referenced to
GND unless otherwise specified.
Note 3: An internal clamp limits the GATE pin to a minimum of 10V above
SOURCE. Driving this pin to voltages beyond the clamp may damage the
device.
Note 4: Guaranteed by design and not subject to test.
Note 5: TUE is the maximum ADC error for any code, given as a
percentage of full scale.
Note 6: UV, OV and FB internal thresholds are given as a percent
difference from the configured operating voltage.
Note 7: EEPROM endurance and retention are guaranteed by design,
characterization and correlation with statistical process controls.
Note 8: EEPROM endurance and retention will be degraded when TJ > 85°C.
Timing Diagram
SDA
SCL
tHD,STA
REPEATED START
CONDITION
tSU,DAT
tHD,DATO
tHD,DATI
tSU,STA tHD,STA tSP
tSP
tSU,STO
tBUF
4282 TD
REPEATED START
CONDITION
For more information www.linear.com/LTC4282
STOP
CONDITION
START
CONDITION
4282f
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5 Page 
LTC4282
Operation
The LTC4282 is designed to turn a board’s supply voltage
on and off in a controlled manner, allowing the board to be
safely inserted or removed from a live backplane. During
normal operation, the gate drivers turn on a pair of parallel
external N-channel MOSFETs to pass power to the load.
The gate driver charge pumps derive their power from
the VDD pin. Also included in the gate drivers are 12.5V
GATE-to-SOURCE clamps to protect the oxide of external
MOSFETs. During start-up the inrush current is tightly
balanced and controlled by using current limit foldback.
Two MOSFETs are used to double the SOA and halve the
RDS(ON) as compared to a single MOSFET. The current limit
(CL) amplifiers monitor the load current with current sense
resistors connected between the SENSE1+, SENSE2+ and
SENSE1–, SENSE2– pins. The CL amplifiers limit the cur-
rent in the load by pulling back on the GATE-to-SOURCE
voltages in an active control loop when the sense voltages
exceed the commanded value.
An overcurrent fault at the output may result in excessive
MOSFET power dissipation during active current limiting.
To limit this power, the CL amplifiers regulate the voltage
between the SENSE1+, SENSE2+ and SENSE1–, SENSE2–
pins at the value set in the ILIM register. When the output
(SOURCE pin) is low, power dissipation is further reduced
by folding back the current limit to 30% of nominal.
The TIMER pin ramps up with 20μA when both current
limit circuits are active. The LTC4282 turns off both GATEs
and registers a fault when the TIMER pin reaches its 1.28V
threshold. At this point the TIMER pin ramps down using
a 5μA current source until the voltage drops below 0.2V
(comparator TM1). The TIMER pin will then ramp up and
down 256 times with 20µA/5µA before indicating that the
external MOSFET has cooled and it is safe to turn on again,
provided overcurrent auto-retry is enabled.
The output voltage is monitored using the SOURCE pin
and the power good (PG) comparator to determine if the
power is available for the load. The power good condition
can be signaled by the GPIO1 pin. The GPIO1 pin may also
be configured to signal power bad, as a general purpose
input (GP comparator), or a general purpose open-drain
output.
GPIO2 and GPIO3 may also be configured as general
purpose inputs or general purpose open-drain outputs.
Additionally the ADC measures these pins with a 1.28V
full-scale. GPIO2 may be configured to pull low to indicate
that the external MOSFETs are in a state of stress when
the MOSFETs are commanded to be on and either the gate
voltages are lower than they should be, or the drain-to-
source voltage exceeds 200mV.
The Functional Diagram shows the monitoring blocks of
the LTC4282. The group of comparators on the left side
includes the undervoltage (UV), overvoltage (OV), and
(ON) comparators. These comparators determine if the
external conditions are valid prior to turning on the GATEs.
But first the two undervoltage lockout circuits, UVLO1
and UVLO2, validate the input supply and the internally
generated 3.3V supply, INTVCC. UVLO2 also generates
the power-up initialization to the logic circuits and copies
the contents of the EEPROM to operating memory after
INTVCC crosses this rising threshold.
Included in the LTC4282 is a pair of 12-/16-bit A/D convert-
ers. One data converter continuously monitors the ADC+
to ADC– voltage, sampling every 16µs and producing a
12-bit result of the average current sense voltage every
65ms. The other data converter is synchronized to the first
one and measures the GPIO voltage and SOURCE voltage
during the same time period. Every time the ADCs finish
taking a measurement, the current sense voltage is mul-
tiplied by the measurement of the SOURCE pin to provide
a power measurement. Every time power is measured, it
is added to an energy accumulator which keeps track of
how much energy has been transmitted to the load. The
energy accumulator can generate an optional alert upon
overflow, and can be pre-set to allow it to overflow after
a given amount of energy has been transmitted. A time
accumulator also keeps track of how many times the
power meter has been incremented; dividing the results
of the energy accumulator by the time accumulator gives
the average system power. The minimum and maximum
measurements of GPIO, SOURCE, ADC+ to ADC– and
power are stored, and optional alerts may be generated
if a measurement is above or below user configurable
8-bit thresholds.
For more information www.linear.com/LTC4282
4282f
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11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LTC4282.PDF ] | |
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