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FSTU32X384QSP 데이터시트 PDF




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부품번호 FSTU32X384QSP 기능
기능 20-Bit Low Power Bus Switch with -2V Undershoot Protection
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FSTU32X384QSP 데이터시트, 핀배열, 회로
May 2002
Revised June 2002
FSTU32X384
20-Bit Low Power Bus Switch
with 2V Undershoot Protection
General Description
The Fairchild Switch FSTU32X384 provides 20 bits of high-
speed CMOS TTL-compatible bus switches. The low On
Resistance of the switch allows inputs to be connected to
outputs without adding propagation delay or generating
additional ground bounce noise. The device is organized
as four 5-bit switches with separate bus enable (OE) sig-
nals. When OE is LOW, the switch is ON and Port A is con-
nected to Port B. When OE is HIGH, the switch is OPEN
and a high-impedance state exists between the two ports.
The A and B Ports are protected against undershoot to
support an extended range to 2.0V below ground.
Fairchild’s integrated Undershoot Hardened Circuit
(UHC) senses undershoot at the I/O and responds by
preventing voltage differentials from developing and turn-
ing the switch on.
Features
s 4switch connection between two ports
s Minimal propagation delay through the switch
s Ultra low power with < 0.1 µA typical ICC
s Zero ground bounce in flow-through mode
s Control inputs compatible with TTL level
s See Application Note AN-5008 for details on
FSTU - Undershoot Protected Fairchild Switch Family
Ordering Code:
Order Number
Package
Number
Package Description
FSTU32X384QSP MQA48A 48-Lead Quarter Size Very Small Outline Package (QVSOP), JEDEC MO-154, 0.150" Wide
Device also available in Tape and Reel. Specify by appending suffix letter Xto the ordering code.
Logic Diagram
UHCis a trademark of Fairchild Semiconductor Corporation.
© 2002 Fairchild Semiconductor Corporation DS500705
www.fairchildsemi.com




FSTU32X384QSP pdf, 반도체, 판매, 대치품
AC Electrical Characteristics
TA = −40°C to +85°C
Symbol
Parameter
CL = 50 pF, RU = RD = 500
VCC = 4.5 5.5V
VCC = 4.0V
Units
Conditions
Figure
Number
Min Max Min Max
tPHL, tPLH Propagation Delay Bus to Bus
(Note 8)
0.25
0.25 ns VI = OPEN
Figures
2, 3
tPZH, tPZL
Output Enable Time
OE1, OE2 to An, Bn
1.0 5.7
6.2 ns VI = 7V for tPZL
VI = OPEN for tPZH
Figures
2, 3
tPHZ, tPLZ
Output Disable Time
OE1, OE2 to An, Bn
1.5 5.2
5.5 ns II = 7V for tPLZ
VI = OPEN for tPHZ
Figures
2, 3
Note 8: This parameter is guaranteed by design but not tested. The bus switch contributes no propagation delay other than the RC delay of the typical On
Resistance of the switch and the 50pF load capacitance, when driven by an ideal voltage the source (zero output impedance).
Capacitance (Note 9)
Symbol
Parameter
CIN Control Input Capacitance
CI/O (OFF) Input/Output Capacitance
Note 9: Capacitance is characterized but not tested.
Typ
Max
Units
Conditions
3 6 pF
VCC = 5.0V
5 13 pF VCC, OE = 5.0V
Undershoot Characteristic (Note 10)
Symbol
Parameter
Min
Typ
Max
Units
Conditions
VOUTU
Output Voltage During Undershoot
2.5 VOH - 0.3
V Figure 1
Note 10: This test is intended to characterize the devices protective capabilities by maintaining output signal integrity during an input transient voltage
undershoot event.
Device Test Conditions
Parameter
VIN
R1 = R2
VTRI
VCC
Value
see Waveform
100K
11.0
5.5
FIGURE 1.
Transient
Units Input Voltage (VIN) Waveform
V
V
V
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FSTU32X384QSP

20-Bit Low Power Bus Switch with -2V Undershoot Protection

Fairchild Semiconductor
Fairchild Semiconductor

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