PDF ST7LITE19B Data sheet ( Hoja de datos )

Número de pieza	ST7LITE19B
Descripción	8-BIT MCU
Fabricantes	STMicroelectronics
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ST7LITE1xB 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, 5 TIMERS, SPI ■ Memories – up to 4 Kbytes single voltage extended Flash (XFlash) Program memory with read-out pro- tection, In-Circuit Programming and In-Appli- cation programming (ICP and IAP). 10K write/ erase cycles guaranteed, data retention: 20 years at 55°C. – 256 bytes RAM – 128 bytes data EEPROM with read-out pro- tection. 300K write/erase cycles guaranteed, data retention: 20 years at 55°C. ■ Clock, Reset and Supply Management – Enhanced reset system – Enhanced low voltage supervisor (LVD) for main supply and an auxiliary voltage detector (AVD) with interrupt capability for implement- ing safe power-down procedures – Clock sources: Internal 1% RC oscillator (on ST7FLITE15B and ST7FLITE19B), crystal/ ceramic resonator or external clock – Internal 32-MHz input clock for Auto-reload timer – Optional x4 or x8 PLL for 4 or 8 MHz internal clock – Five Power Saving Modes: Halt, Active-Halt, Auto Wake-up from Halt, Wait and Slow ■ I/O Ports – Up to 17 multifunctional bidirectional I/O lines – 7 high sink outputs ■ 5 Timers – Configurable watchdog timer – Two 8-bit Lite Timers with prescaler, 1 realtime base and 1 input capture – Two 12-bit Auto-reload Timers with 4 PWM Device Summary DIP20 SO20 QFN20 DIP16 SO16 300” outputs, 1 input capture, 4 output compare and one pulse functions ■ Communication Interface – SPI synchronous serial interface ■ Interrupt Management – 12 interrupt vectors plus TRAP and RESET – 15 external interrupt lines (on 4 vectors) ■ Analog Comparator ■ A/D Converter – 7 input channels – Fixed gain Op-amp – 13-bit precision for 0 to 430 mV (@ 5V VDD) – 10-bit precision for 430 mV to 5V (@ 5V VDD) ■ Instruction Set – 8-bit data manipulation – 63 basic instructions with illegal opcode de- tection – 17 main addressing modes – 8 x 8 unsigned multiply instructions ■ Development Tools – Full hardware/software development package – DM (Debug Module) Features ST7LITE10B ST7LITE15B ST7LITE19B Program memory - bytes 2K/4K RAM (stack) - bytes 256 (128) Data EEPROM - bytes - - 128 Peripherals Lite Timer with Wdg, Autoreload Lite Timer with Wdg, Autoreload Timer with 32-MHz input clock, SPI, Timer, SPI, 10-bit ADC with Op-Amp 10-bit ADC with Op-Amp, Analog Comparator Operating Supply 2.7V to 5.5V CPU Frequency Up to 8Mhz(w/ ext OSC at 16MHz) Up to 8Mhz (w/ ext OSC at 16MHz or int 1MHz RC 1%, PLLx8/4MHz) Operating Temperature -40°C to +85°C / -40°C to +125°C Packages SO20 300”, DIP20, SO16 300”, DIP16 SO20 300”, DIP20, SO16 300”, DIP16, QFN20 Rev 6 June 2008 1/159 1 1 page ST7LITE1xB 2 PIN DESCRIPTION Figure 2. 20-Pin SO and DIP Package Pinout VSS VDD RESET COMPIN+/SS/AIN0/PB0 SCK/AIN1/PB1 MISO/AIN2/PB2 MOSI/AIN3/PB3 COMPIN-/CLKIN/AIN4/PB4 AIN5/PB5 AIN6/PB6 1 2 3 4 5 ei3 6 7 8 ei2 9 10 20 19 18 ei0 17 16 15 14 ei1 13 12 11 OSC1/CLKIN/PC0 OSC2/PC1 PA0 (HS)/LTIC PA1 (HS)/ATIC PA2 (HS)/ATPWM0 PA3 (HS)/ATPWM1 PA4 (HS)/ATPWM2 PA5 (HS)/ATPWM3/ICCDATA PA6/MCO/ICCCLK/BREAK PA7(HS)/COMPOUT Figure 3. 20-Pin QFN Package Pinout (HS) 20mA High sink capability eix associated external interrupt vector RESET COMPIN+/SS/AIN0/PB0 SCK/AIN1/PB1 MISO/AIN2/PB2 MOSI/AIN3/PB3 COMPIN-/CLKIN/AIN4/PB4 20 19 18 17 1 16 2 3 ei3 15 ei0 14 4 13 5 ei2 6 78 12 ei1 11 9 10 PA0 (HS)/LTIC PA1 (HS)/ATIC PA2 (HS)/ATPWM0 PA3 (HS)/ATPWM1 PA4 (HS)/ATPWM2 PA5 (HS)/ATPWM3/ICCDATA (HS) 20mA High sink capability eix associated external interrupt vector 5/159 1 5 Page ST7LITE1xB Address Block Register Label Register Name Reset Status Remarks 0002Fh FLASH FCSR 00030h EEPROM EECSR 0031h 0032h 0033h SPIDR SPI SPICR SPICSR 0034h 0035h 0036h ADC ADCCSR ADCDRH ADCDRL 0037h ITC EICR 0038h MCC MCCSR 0039h Clock and RCCR 003Ah Reset SICSR 003Bh PLL clock select PLLTST 003Ch ITC EISR 003Dh to 0048h 0049h 004Ah AWU AWUPR AWUCSR 004Bh 004Ch 004Dh 004Eh 004Fh 0050h 0051h DM3) DMCR DMSR DMBK1H DMBK1L DMBK2H DMBK2L DMCR2 0052h to 007Fh Flash Control/Status Register Data EEPROM Control/Status Register SPI Data I/O Register SPI Control Register SPI Control Status Register A/D Control Status Register A/D Data Register High A/D Amplifier Control/Data Low Register External Interrupt Control Register Main Clock Control/Status Register RC oscillator Control Register System Integrity Control/Status Register 00h 00h xxh 0xh 00h 00h xxh 0xh 00h 00h FFh 0110 0xx0b R/W R/W R/W R/W R/W R/W Read Only R/W R/W R/W R/W R/W PLL test register 00h R/W External Interrupt Selection Register 0Ch R/W Reserved area (12 bytes) AWU Prescaler Register AWU Control/Status Register DM Control Register DM Status Register DM Breakpoint Register 1 High DM Breakpoint Register 1 Low DM Breakpoint Register 2 High DM Breakpoint Register 2 Low DM Control Register 2 FFh R/W 00h R/W 00h R/W 00h R/W 00h R/W 00h R/W 00h R/W 00h R/W 00h R/W Reserved area (46 bytes) Legend: x=undefined, R/W=read/write Notes: 1. The contents of the I/O port DR registers are readable only in output configuration. In input configura- tion, the values of the I/O pins are returned instead of the DR register contents. 2. The bits associated with unavailable pins must always keep their reset value. 3. For a description of the Debug Module registers, see ICC protocol reference manual. 11/159 1 11 Page

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