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uPSD3312D-40T6 데이터시트 PDF




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부품번호 uPSD3312D-40T6 기능
기능 Fast 8032 MCU
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uPSD3312D-40T6 데이터시트, 핀배열, 회로
uPSD33XX
uPSD33XX (Turbo Series)
Fast 8032 MCU with Programmable Logic
PRELIMINARY DATA
FEATURES SUMMARY
FAST 8-BIT TURBO 8032 MCU, 40MHz
– Advanced core, 4-clocks per instruction
– 10 MIPs peak performance at 40MHz (5V)
– JTAG Debug and In-System
Programming
– Branch Cache & 6 instruction Prefetch
Queue
– Dual XDATA pointers with auto incr & decr
– Compatible with 3rd party 8051 tools
DUAL FLASH MEMORIES WITH MEMORY
MANAGEMENT
– Place either memory into 8032 program
address space or data address space
– READ-while-WRITE operation for In-
Application Programming and EEPROM
emulation
– Single voltage program and erase
– 100K guaranteed erase cycles, 15-year
retention
CLOCK, RESET, AND SUPPLY
MANAGEMENT
– SRAM is Battery Backup capable
– Flexible 8-level CPU clock divider register
– Normal, Idle, and Power Down Modes
– Power-on and Low Voltage reset
supervisor
– Programmable Watchdog Timer
PROGRAMMABLE LOGIC, GENERAL
PURPOSE
– 16 macrocells
– Create shifters, state machines, chip-
selects, glue-logic to keypads, panels,
LCDs, others
COMMUNICATION INTERFACES
– I2C Master/Slave controller, 833KHz
– SPI Master controller, 1MHz
– Two UARTs with independent baud rate
– IrDA protocol support up to 115K baud
– Up to 46 I/O, 5V tolerant on 3.3V
uPSD33XXV
Figure 1. Packages
TQFP52 (T)
52-lead, Thin,
Quad, Flat
TQFP80 (U)
80-lead, Thin,
Quad, Flat
A/D CONVERTER
– Eight Channels, 10-bit resolution, 8µs
TIMERS AND INTERRUPTS
– Three 8032 standard 16-bit timers
– Programmable Counter Array (PCA), six
16-bit modules for PWM, CAPCOM, and
timers
– 8/10/16-bit PWM operation
– 11 Interrupt sources with two external
interrupt pins
OPERATING VOLTAGE SOURCE (±10%)
– 5V devices use both 5.0V and 3.3V
sources
– 3.3V devices use only 3.3V source
May 2004
1/228
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.




uPSD3312D-40T6 pdf, 반도체, 판매, 대치품
uPSD33XX
DUAL DATA POINTERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Data Pointer Control Register, DPTC (85h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Data Pointer Mode Register, DPTM (86h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
DEBUG UNIT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
INTERRUPT SYSTEM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Individual Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
MCU CLOCK GENERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
MCU_CLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
PERIPH_CLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Power-down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Reduced Frequency Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
OSCILLATOR AND EXTERNAL COMPONENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
I/O PORTS of MCU MODULE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
MCU Port Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
MCU BUS INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Bus Read Cycles (PSEN or RD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Bus Write Cycles (WR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Controlling the PFQ and BC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
SUPERVISORY FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
External Reset Input Pin, RESET_IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Low VCC Voltage Detect, LVD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Power-up Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
JTAG Debug Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Watchdog Timer, WDT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
STANDARD 8032 TIMER/COUNTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Standard Timer SFRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
SFR, TCON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
SFR, TMOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Timer 0 and Timer 1 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Timer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
SERIAL UART INTERFACES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
UART Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
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uPSD3312D-40T6 전자부품, 판매, 대치품
uPSD33XX
SUMMARY DESCRIPTION
The Turbo uPSD33XX Series combines a power-
ful 8051-based microcontroller with a flexible
memory structure, programmable logic, and a rich
peripheral mix to form an ideal embedded control-
ler. At it’s core is a fast 4-cycle 8032 MCU with a
6-byte instruction prefetch queue (PFQ) and a 4-
entry fully associative branching cache (BC) to
maximize MCU performance, enabling loops of
code in smaller localities to execute extremely
fast. Code development is easily managed without
a hardware In-Circuit Emulator by using the serial
JTAG debug interface. JTAG is also used for In-
System Programming (ISP) in as little as 10 sec-
onds, perfect for manufacturing and lab develop-
ment. The 8032 core is coupled to Programmable
System Device (PSD) architecture to optimize the
8032 memory structure, offering two independent
Figure 2. General Block Diagram
banks of Flash memory that can be placed at vir-
tually any address within 8032 program or data ad-
dress space, and easily paged beyond 64K bytes
using on-chip programmable decode logic. Dual
Flash memory banks provide a robust solution for
remote product updates in the field through In-Ap-
plication Programming (IAP). Dual Flash banks
also support EEPROM emulation, eliminating the
need for external EEPROM chips. General pur-
pose programmable logic (PLD) is included to
build an endless variety of glue-logic, saving exter-
nal logic devices. The PLD is configured using the
software development tool, PSDsoft Express,
available from the web at www.st.com/psm, at no
charge. The uPSD33XX also includes supervisor
functions such as a programmable watchdog timer
and low-voltage reset.
P3.0:7
P1.0:7
P4.0:7
(3) 16-bit
Timer/
Counters
(2)
External
Interrupts
Turbo
8032
Core
PFQ
&
BC
I2C
UART0
(8) GPIO, Port 3
(8) GPIO, Port 1
(8) 10-bit ADC
Optional IrDA
Encoder/Decoder
UART1
SPI
16-bit PCA
(6) PWM, CAPCOM, TIMER
(8) GPIO, Port 4
uPSD33XX
Programmable
Decode and
Page Logic
1st Flash Memory:
64K, 128K,
or 256K Bytes
2nd Flash Memory:
16K or 32K Bytes
SRAM:
2K, 8K, or 32K Bytes
General
Purpose
Programmable
Logic,
16 Macrocells
(8) GPIO, Port A
(80-pin only)
(8) GPIO, Port B
(2) GPIO, Port D
(4) GPIO, Port C
JTAG ICE and ISP
8032 Address/Data/Control Bus
(80-pin device only)
Supervisor:
Watchdog and Low-Voltage Reset
VCC, VDD, GND, Reset, Crystal In
PA0:7
PB0:7
PD1:2
PC0:7
MCU
Bus
Dedicated
Pins
AI08875
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관련 데이터시트

부품번호상세설명 및 기능제조사
UPSD3312D-40T6

Fast 8032 MCU

STMicroelectronics
STMicroelectronics
uPSD3312D-40T6

Fast 8032 MCU

STMicroelectronics
STMicroelectronics

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