Datasheet.kr   

P8X32A-Q44 데이터시트 PDF




Parallax에서 제조한 전자 부품 P8X32A-Q44은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

PDF 형식의 P8X32A-Q44 자료 제공

부품번호 P8X32A-Q44 기능
기능 8-Cog Multiprocessor Microcontroller
제조업체 Parallax
로고 Parallax 로고


P8X32A-Q44 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.




전체 30 페이지수

미리보기를 사용할 수 없습니다

P8X32A-Q44 데이터시트, 핀배열, 회로
PropellerP8X32A Datasheet
8-Cog Multiprocessor Microcontroller
1.0 PRODUCT OVERVIEW
1.1. Introduction
The Propeller chip is designed to provide high-speed processing for embedded systems while maintaining low current
consumption and a small physical footprint. In addition to being fast, the Propeller chip provides flexibility and power
through its eight processors, called cogs, that can perform simultaneous tasks independently or cooperatively, all while
maintaining a relatively simple architecture that is easy to learn and utilize. Two programming languages are available: Spin
(a high-level object-based language) and Propeller Assembly. Both include custom commands to easily manage the
Propeller chip’s unique features.
Figure 1: Propeller P8X32A Block Diagram
1.2. Stock Codes
Table 1: Propeller Chip Stock Codes
Device
Stock #
Package Type
I/O Power
Pins Requirements
External
Clock
Speed
Internal RC
Oscillator
Internal
Execution
Speed
P8X32A-D40
P8X32A-Q44
P8X32A-M44
40-pin DIP
44-pin LQFP
44-pin QFN
32
CMOS
3.3 volts DC
DC to 80
MHz
12 MHz or
20 kHz*
*Approximate; may range from 8 MHz – 20 MHz, or 13 kHz – 33 kHz, respectively.
0 to 160 MIPS
(20 MIPS/cog)
Global
ROM/RAM
64 K bytes;
32768 bytes
ROM / 32768
bytes RAM
Cog RAM
512 x 32 bits
per cog
Parallax, Propeller, Spin, and the Parallax and Propeller logos are trademarks of Parallax, Inc. All other trademarks are the property of their respective holders.
Copyright © Parallax Inc.
Page 1 of 37
Rev 1.2 4/24/2009




P8X32A-Q44 pdf, 반도체, 판매, 대치품
Propeller™ P8X32A Datasheet
2.0 CONNECTION DIAGRAMS
2.1. Pin Assignments
www.parallax.com
LQFP and QFN Packages
DIP Package
2.2. Pin Descriptions
Pin Name
Direction
Table 2: Pin Descriptions
Description
General purpose I/O Port A. Can source/sink 40 mA each at 3.3 VDC. CMOS level logic with threshold
of ½ VDD or 1.6 VDC @ 3.3 VDC.
P0 – P31
I/O
The pins shown below have a special purpose upon power-up/reset but are general purpose I/O
afterwards.
P28 - I2C SCL connection to optional, external EEPROM.
P29 - I2C SDA connection to optional, external EEPROM.
P30 - Serial Tx to host.
P31 - Serial Rx from host.
VDD
---
3.3 volt power (2.7 – 3.6 VDC)
VSS
BOEn
RESn
XI
XO
---
I
I/O
I
O
Ground
Brown Out Enable (active low). Must be connected to either VDD or VSS. If low, RESn becomes a
weak output (delivering VDD through 5 k) for monitoring purposes but can still be driven low to cause
reset. If high, RESn is CMOS input with Schmitt Trigger.
Reset (active low). When low, resets the Propeller chip: all cogs disabled and I/O pins floating.
Propeller restarts 50 ms after RESn transitions from low to high.
Crystal Input. Can be connected to output of crystal/oscillator pack (with XO left disconnected), or to
one leg of crystal (with XO connected to other leg of crystal or resonator) depending on CLK Register
settings. No external resistors or capacitors are required.
Crystal Output. Provides feedback for an external crystal, or may be left disconnected depending on
CLK Register settings. No external resistors or capacitors are required.
Copyright © Parallax Inc.
Page 4 of 37
Rev 1.2 4/24/2009

4페이지










P8X32A-Q44 전자부품, 판매, 대치품
Propeller™ P8X32A Datasheet
4.3. Cogs (processors)
The Propeller contains eight (8) identical, independent
processors, called cogs, numbered 0 to 7. Each cog
contains a Processor block, local 2 KB RAM configured
as 512 longs (512 x 32 bits), two advanced counter
modules with PLLs, a Video Generator, I/O Output
Register, I/O Direction Register, and other registers not
shown in the Block Diagram.
All eight cogs are driven from the System Clock; they
each maintain the same time reference and all active cogs
execute instructions simultaneously. They also all have
access to the same shared resources.
Cogs can be started and stopped at run time and can be
programmed to perform tasks simultaneously, either
independently or with coordination from other cogs
through Main RAM. Each cog has its own RAM, called
Cog RAM, which contains 512 registers of 32 bits each.
The Cog RAM is all general purpose RAM except for the
last 16 registers, which are special purpose registers, as
described in Table 15 on page 16.
4.4. Hub
To maintain system integrity, mutually-exclusive
resources must not be accessed by more than one cog at a
time. The Hub controls access to mutually-exclusive
resources by giving each cog a turn in a “round robin”
fashion from Cog 0 through Cog 7 and back to Cog 0
again. The Hub and its bus run at half the System Clock
rate, giving a cog access to mutually-exclusive resources
once every 16 System Clock cycles. Hub instructions, the
Propeller Assembly instructions that access mutually-
exclusive resources, require 7 cycles to execute but they
first need to be synchronized to the start of the Hub
Access Window.
Figure 2: Cog-Hub
Interaction – Best Case
Scenario
www.parallax.com
It takes up to 15 cycles (16 minus 1, if we just missed it)
to synchronize to the Hub Access Window plus 7 cycles
to execute the hub instruction, so hub instructions take
from 7 to 22 cycles to complete.
Figure 2 and Figure 3 show examples where Cog 0 has a
hub instruction to execute. Figure 2 shows the best-case
scenario; the hub instruction was ready right at the start of
that cog’s access window. The hub instruction executes
immediately (7 cycles) leaving an additional 9 cycles for
other instructions before the next Hub Access Window
arrives.
Figure 3 shows the worst-case scenario; the hub
instruction was ready on the cycle right after the start of
Cog 0’s access window; it just barely missed it. The cog
waits until the next Hub Access Window (15 cycles later)
then the hub instruction executes (7 cycles) for a total of
22 cycles for that hub instruction. Again, there are 9
additional cycles after the hub instruction for other
instructions to execute before the next Hub Access
Window arrives. To get the most efficiency out of
Propeller Assembly routines that have to frequently
access mutually-exclusive resources, it can be beneficial
to interleave non-hub instructions with hub instructions to
lessen the number of cycles waiting for the next Hub
Access Window. Since most Propeller Assembly
instructions take 4 clock cycles, two such instructions can
be executed in between otherwise contiguous hub
instructions.
Keep in mind that a particular cog’s hub instructions do
not, in any way, interfere with other cogs’ instructions
because of the Hub mechanism. Cog 1, for example, may
start a hub instruction during System Clock cycle 2, in
both of these examples, possibly overlapping its execution
with that of Cog 0 without any ill effects. Meanwhile, all
other cogs can continue executing non-hub instructions,
or awaiting their individual hub access windows
regardless of what the others are doing.
Figure 3: Cog-Hub
Interaction – Worst Case
Scenario
Copyright © Parallax Inc.
Page 7 of 37
Rev 1.2 4/24/2009

7페이지


구       성 총 30 페이지수
다운로드[ P8X32A-Q44.PDF 데이터시트 ]

당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는

포괄적인 데이터시트를 제공합니다.


구매 문의
일반 IC 문의 : 샘플 및 소량 구매
-----------------------------------------------------------------------

IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한
광범위한 전력 반도체를 판매합니다.

전력 반도체 전문업체

상호 : 아이지 인터내셔날

사이트 방문 :     [ 홈페이지 ]     [ 블로그 1 ]     [ 블로그 2 ]



관련 데이터시트

부품번호상세설명 및 기능제조사
P8X32A-Q44

8-Cog Multiprocessor Microcontroller

Parallax
Parallax

DataSheet.kr       |      2020   |     연락처      |     링크모음      |      검색     |      사이트맵