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74HC165 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 74HC165
기능 8-bit parallel-in/serial out shift register
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74HC165 데이터시트, 핀배열, 회로
74HC165; 74HCT165
8-bit parallel-in/serial out shift register
Rev. 03 — 14 March 2008
Product data sheet
1. General description
The 74HC165; 74HCT165 are high-speed Si-gate CMOS devices that comply with
JEDEC standard no. 7A. They are pin compatible with Low-power Schottky TTL (LSTTL).
The 74HC165; 74HCT165 are 8-bit parallel-load or serial-in shift registers with
complementary serial outputs (Q7 and Q7) available from the last stage. When the
parallel load (PL) input is LOW, parallel data from the D0 to D7 inputs are loaded into the
register asynchronously.
When PL is HIGH, data enters the register serially at the DS input and shifts one place to
the right (Q0 Q1 Q2, etc.) with each positive-going clock transition. This feature
allows parallel-to-serial converter expansion by tying the Q7 output to the DS input of the
succeeding stage.
The clock input is a gated-OR structure which allows one input to be used as an active
LOW clock enable (CE) input. The pin assignment for the CP and CE inputs is arbitrary
and can be reversed for layout convenience. The LOW-to-HIGH transition of input CE
should only take place while CP HIGH for predictable operation. Either the CP or the CE
should be HIGH before the LOW-to-HIGH transition of PL to prevent shifting the data
when PL is activated.
2. Features
I Asynchronous 8-bit parallel load
I Synchronous serial input
I Complies with JEDEC standard no. 7A
I ESD protection:
N HBM JESD22-A114E exceeds 2000 V
N MM JESD22-A115-A exceeds 200 V
I Specified from 40 °C to +85 °C and from 40 °C to +125 °C
3. Applications
I Parallel-to-serial data conversion




74HC165 pdf, 반도체, 판매, 대치품
NXP Semiconductors
74HC165; 74HCT165
8-bit parallel-in/serial out shift register
6.2 Pin description
Table 2.
Symbol
PL
CP
Q7
GND
Q7
DS
D0 to D7
CE
VCC
Pin description
Pin
1
2
7
8
9
10
11, 12, 13, 14, 3, 4, 5, 6
15
16
Description
asynchronous parallel load input (active LOW)
clock input (LOW-to-HIGH edge-triggered)
complementary output from the last stage
ground (0 V)
serial output from the last stage
serial data input
parallel data inputs (also referred to as Dn)
clock enable input (active LOW)
positive supply voltage
7. Functional description
Table 3. Function table[1]
Operating modes Inputs
Qn registers
Outputs
PL CE CP DS D0 to D7 Q0 Q1 to Q6 Q7 Q7
parallel load
L
X
X
X
L
L
L to L L
H
L X X X H H H to H H L
serial shift
HL l
X
L
q0 to q5 q6
q6
HL
h
X
H
q0 to q5 q6
q6
HL l
X
L
q0 to q5 q6
q6
H
L
h
X
H
q0 to q5 q6
q6
hold “do nothing” H H X X X q0 q1 to q6 q7 q7
H X H X X q0 q1 to q6 q7 q7
[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
q = state of the referenced output one set-up time prior to the LOW-to-HIGH clock transition;
X = don’t care;
= LOW-to-HIGH clock transition.
74HC_HCT165_3
Product data sheet
Rev. 03 — 14 March 2008
© NXP B.V. 2008. All rights reserved.
4 of 22

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74HC165 전자부품, 판매, 대치품
NXP Semiconductors
74HC165; 74HCT165
8-bit parallel-in/serial out shift register
Table 6. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 °C
40 °C to +85 °C 40 °C to +125 °C Unit
Min Typ Max Min Max Min Max
VOH HIGH-level
VI = VIH or VIL
output voltage
IO = 20 µA; VCC = 2.0 V 1.9 2.0
-
1.9
-
1.9
IO = 20 µA; VCC = 4.5 V 4.4 4.5 -
4.4
-
4.4
IO = 20 µA; VCC = 6.0 V 5.9 6.0 -
5.9
-
5.9
IO = 4.0 mA; VCC = 4.5 V 3.98 4.32 -
3.84
-
3.7
IO = 5.2 mA; VCC = 6.0 V 5.48 5.81 -
5.34
-
5.2
VOL LOW-level
VI = VIH or VIL
output voltage
IO = 20 µA; VCC = 2.0 V
-
0 0.1
-
0.1
-
IO = 20 µA; VCC = 4.5 V - 0 0.1 - 0.1 -
IO = 20 µA; VCC = 6.0 V - 0 0.1 - 0.1 -
IO = 4.0 mA; VCC = 4.5 V
- 0.15 0.26
-
0.33
-
IO = 5.2 mA; VCC = 6.0 V
- 0.16 0.26
-
0.33
-
II input leakage VI = VCC or GND;
current
VCC = 6.0 V
-
- ±0.1
-
±1
-
ICC
supply current VI = VCC or GND; IO = 0 A;
-
- 8.0
-
80
-
VCC = 6.0 V
CI input
capacitance
- 3.5 -
-
-
-
-V
-V
-V
-V
-V
0.1 V
0.1 V
0.1 V
0.4 V
0.4 V
±1 µA
160 µA
- pF
74HCT165
VIH HIGH-level VCC = 4.5 V to 5.5 V
input voltage
2.0 1.6 -
2.0
-
2.0
-V
VIL LOW-level VCC = 4.5 V to 5.5 V
input voltage
- 1.2 0.8
-
0.8
-
0.8 V
VOH HIGH-level
VI = VIH or VIL; VCC = 4.5 V
output voltage
IO = 20 µA
4.4 4.5 -
4.4
-
4.4
-V
IO = 4.0 mA
3.98 4.32 - 3.84
-
3.7
-V
VOL LOW-level
VI = VIH or VIL; VCC = 4.5 V
output voltage
IO = 20 µA; VCC = 4.5 V
-
0 0.1
-
0.1
-
0.1 V
IO = 5.2 mA; VCC = 6.0 V
- 0.16 0.26
-
0.33
-
0.4 V
II input leakage VI = VCC or GND;
current
VCC = 6.0 V
-
- ±0.1
-
±1
-
±1 µA
ICC
supply current VI = VCC or GND; IO = 0 A;
-
- 8.0
-
80
-
160 µA
VCC = 6.0 V
ICC
additional
supply current
per input pin;
VI = VCC 2.1 V;
other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V
Dn and DS inputs
- 35 126 - 157.5 - 171.5 µA
CP CE, and PL inputs
- 65 234 - 292.5 - 318.5 µA
CI input
capacitance
- 3.5 -
-
-
-
- pF
74HC_HCT165_3
Product data sheet
Rev. 03 — 14 March 2008
© NXP B.V. 2008. All rights reserved.
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