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XC2VPX70 데이터시트 PDF




Xilinx에서 제조한 전자 부품 XC2VPX70은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 XC2VPX70 자료 제공

부품번호 XC2VPX70 기능
기능 Virtex-II Pro and Virtex-II Pro X Platform FPGAs
제조업체 Xilinx
로고 Xilinx 로고


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XC2VPX70 데이터시트, 핀배열, 회로
Product Not Recommended For New Designs
1
R Virtex-II Pro and Virtex-II Pro X Platform FPGAs:
Complete Data Sheet
DS083 (v5.0) June 21, 2011
0
Product Specification
Module 1:
Introduction and Overview
10 pages
• Summary of Features
• General Description
• Architecture
• IP Core and Reference Support
• Device/Package Combinations and Maximum I/O
• Ordering Information
Module 2:
Functional Description
60 pages
• Functional Description: RocketIO™ X Multi-Gigabit
Transceiver
• Functional Description: RocketIO Multi-Gigabit
Transceiver
• Functional Description: Processor Block
• Functional Description: PowerPC™ 405 Core
• Functional Description: FPGA
- Input/Output Blocks (IOBs)
- Digitally Controlled Impedance (DCI)
- On-Chip Differential Termination
- Configurable Logic Blocks (CLBs)
- 3-State Buffers
- CLB/Slice Configurations
- 18-Kb Block SelectRAM™ Resources
- 18-Bit x 18-Bit Multipliers
- Global Clock Multiplexer Buffers
- Digital Clock Manager (DCM)
• Routing
• Configuration
Module 3:
DC and Switching Characteristics
59 pages
• Electrical Characteristics
• Performance Characteristics
• Switching Characteristics
• Pin-to-Pin Output Parameter Guidelines
• Pin-to-Pin Input Parameter Guidelines
• DCM Timing Parameters
• Source-Synchronous Switching Characteristics
Module 4:
Pinout Information
302 pages
• Pin Definitions
• Pinout Tables
- FG256/FGG256 Wire-Bond Fine-Pitch BGA Package
- FG456/FGG456 Wire-Bond Fine-Pitch BGA Package
- FG676/FGG676 Wire-Bond Fine-Pitch BGA Package
- FF672 Flip-Chip Fine-Pitch BGA Package
- FF896 Flip-Chip Fine-Pitch BGA Package
- FF1148 Flip-Chip Fine-Pitch BGA Package
- FF1152 Flip-Chip Fine-Pitch BGA Package
- FF1517 Flip-Chip Fine-Pitch BGA Package
- FF1696 Flip-Chip Fine-Pitch BGA Package
- FF1704 Flip-Chip Fine-Pitch BGA Package
IMPORTANT NOTE: Page, figure, and table numbers begin at 1 for each module, and each module has its own Revision
History at the end. Use the PDF "Bookmarks" pane for easy navigation in this volume.
© 2000–2011 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. PowerPC is
a trademark of IBM Corp. and is used under license. All other trademarks are the property of their respective owners.
DS083 (v5.0) June 21, 2011
Product Specification
www.xilinx.com
1




XC2VPX70 pdf, 반도체, 판매, 대치품
Product Not Recommended For New Designs
R Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Introduction and Overview
· HyperTransport (LDT) I/O with current driver
buffers
· Built-in DDR input and output registers
- Proprietary high-performance SelectLink
technology for communications between Xilinx
devices
· High-bandwidth data path
· Double Data Rate (DDR) link
· Web-based HDL generation methodology
• SRAM-Based In-System Configuration
- Fast SelectMAP™ configuration
- Triple Data Encryption Standard (DES) security
option (bitstream encryption)
- IEEE 1532 support
- Partial reconfiguration
- Unlimited reprogrammability
- Readback capability
• Supported by Xilinx Foundation™ and Alliance
Series™ Development Systems
- Integrated VHDL and Verilog design flows
- ChipScope™ Integrated Logic Analyzer
• 0.13 µm Nine-Layer Copper Process with 90 nm
High-Speed Transistors
• 1.5V (VCCINT) core power supply, dedicated 2.5V
VCCAUX auxiliary and VCCO I/O power supplies
• IEEE 1149.1 Compatible Boundary-Scan Logic Support
• Flip-Chip and Wire-Bond Ball Grid Array (BGA)
Packages in Standard 1.00 mm Pitch.
• Wire-Bond BGA Devices Available in Pb-Free
Packaging (www.xilinx.com/pbfree)
• Each Device 100% Factory Tested
General Description
The Virtex-II Pro and Virtex-II Pro X families contain plat-
form FPGAs for designs that are based on IP cores and
customized modules. The family incorporates multi-gigabit
transceivers and PowerPC CPU blocks in Virtex-II Pro
Series FPGA architecture. It empowers complete solutions
for telecommunication, wireless, networking, video, and
DSP applications.
The leading-edge 0.13 µm CMOS nine-layer copper pro-
cess and Virtex-II Pro architecture are optimized for high
performance designs in a wide range of densities. Combin-
ing a wide variety of flexible features and IP cores, the
Virtex-II Pro family enhances programmable logic design
capabilities and is a powerful alternative to mask-pro-
grammed gate arrays.
Architecture
Array Overview
Virtex-II Pro and Virtex-II Pro X devices are user-program-
mable gate arrays with various configurable elements and
embedded blocks optimized for high-density and high-per-
formance system designs. Virtex-II Pro devices implement
the following functionality:
• Embedded high-speed serial transceivers enable data
bit rate up to 3.125 Gb/s per channel (RocketIO) or
6.25 Gb/s (RocketIO X).
• Embedded IBM PowerPC 405 RISC processor blocks
provide performance up to 400 MHz.
• SelectIO-Ultra blocks provide the interface between
package pins and the internal configurable logic. Most
popular and leading-edge I/O standards are supported
by the programmable IOBs.
• Configurable Logic Blocks (CLBs) provide functional
elements for combinatorial and synchronous logic,
including basic storage elements. BUFTs (3-state
buffers) associated with each CLB element drive
dedicated segmentable horizontal routing resources.
• Block SelectRAM+ memory modules provide large
18 Kb storage elements of True Dual-Port RAM.
• Embedded multiplier blocks are 18-bit x 18-bit
dedicated multipliers.
• Digital Clock Manager (DCM) blocks provide
self-calibrating, fully digital solutions for clock
distribution delay compensation, clock multiplication
and division, and coarse- and fine-grained clock phase
shifting.
A new generation of programmable routing resources called
Active Interconnect Technology interconnects all these ele-
ments. The general routing matrix (GRM) is an array of rout-
ing switches. Each programmable element is tied to a
switch matrix, allowing multiple connections to the general
routing matrix. The overall programmable interconnection is
hierarchical and supports high-speed designs.
All programmable elements, including the routing
resources, are controlled by values stored in static memory
cells. These values are loaded in the memory cells during
configuration and can be reloaded to change the functions
of the programmable elements.
Features
This section briefly describes Virtex-II Pro / Virtex-II Pro X
features. For more details, refer to Virtex-II Pro and
Virtex-II Pro X Platform FPGAs: Functional Description.
RocketIO / RocketIO X MGT Cores
The RocketIO and RocketIO X Multi-Gigabit Transceivers
are flexible parallel-to-serial and serial-to-parallel embed-
ded transceiver cores used for high-bandwidth interconnec-
tion between buses, backplanes, or other subsystems.
Multiple user instantiations in an FPGA are possible,
providing up to 100 Gb/s (RocketIO) or 170 Gb/s
(RocketIO X) of full-duplex raw data transfer. Each channel
can be operated at a maximum data transfer rate of
3.125 Gb/s (RocketIO) or 6.25 Gb/s (RocketIO X).
DS083 (v5.0) June 21, 2011
Product Specification
www.xilinx.com
Module 1 of 4
3

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XC2VPX70 전자부품, 판매, 대치품
Product Not Recommended For New Designs
R Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Introduction and Overview
implemented. In system mode, a Virtex-II Pro device will
continue to function while executing non-test Bound-
ary-Scan instructions. In test mode, Boundary-Scan test
instructions control the I/O pins for testing purposes. The
Virtex-II Pro Test Access Port (TAP) supports BYPASS,
PRELOAD, SAMPLE, IDCODE, and USERCODE non-test
instructions. The EXTEST, INTEST, and HIGHZ test instruc-
tions are also supported.
Configuration
Virtex-II Pro / Virtex-II Pro devices are configured by load-
ing the bitstream into internal configuration memory using
one of the following modes:
• Slave-serial mode
• Master-serial mode
• Slave SelectMAP mode
• Master SelectMAP mode
• Boundary-Scan mode (IEEE 1532)
A Data Encryption Standard (DES) decryptor is available
on-chip to secure the bitstreams. One or two triple-DES key
sets can be used to optionally encrypt the configuration data.
The Xilinx System Advanced Configuration Enviornment
(System ACE) family offers high-capacity and flexible solu-
tion for FPGA configuration as well as program/data storage
for the processor. See DS080, System ACE CompactFlash
Solution for more information.
Readback and Integrated Logic Analyzer
Configuration data stored in Virtex-II Pro / Virtex-II Pro con-
figuration memory can be read back for verification. Along
with the configuration data, the contents of all flip-flops and
latches, distributed SelectRAM+, and block SelectRAM+
memory resources can be read back. This capability is use-
ful for real-time debugging.
The Xilinx ChipScope Integrated Logic Analyzer (ILA) cores
and Integrated Bus Analyzer (IBA) cores, along with the
ChipScope Pro Analyzer software, provide a complete solu-
tion for accessing and verifying user designs within
Virtex-II Pro devices.
IP Core and Reference Support
Intellectual Property is part of the Platform FPGA solution.
In addition to the existing FPGA fabric cores, the list below
shows some of the currently available hardware and soft-
ware intellectual properties specially developed for
Virtex-II Pro / Virtex-II Pro X by Xilinx. Each IP core is mod-
ular, portable, Real-Time Operating System (RTOS) inde-
pendent, and CoreConnect compatible for ease of design
migration. Refer to www.xilinx.com/ipcenter for the latest
and most complete list of cores.
Hardware Cores
• Bus Infrastructure cores (arbiters, bridges, and more)
• Memory cores (DDR, Flash, and more)
• Peripheral cores (UART, IIC, and more)
• Networking cores (ATM, Ethernet, and more)
Software Cores
• Boot code
• Test code
• Device drivers
• Protocol stacks
• RTOS integration
• Customized board support package
DS083 (v5.0) June 21, 2011
Product Specification
www.xilinx.com
Module 1 of 4
6

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