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PDF HY628400LG Data sheet ( Hoja de datos )
| Número de pieza | HY628400LG | |
| Descripción | 512K x 8bit CMOS SRAM | |
| Fabricantes | Hynix Semiconductor | |
| Logotipo |  |
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HY628400 Series
512Kx8bit CMOS SRAM
DESCRIPTION
The HY628400 is a high-speed, low power and
4M bits CMOS SRAM organized as 524,288
words by 8 bits. The HY628400 uses Hyundai's
high performance twin tub CMOS process
technology and was designed for high-speed and
low power circuit technology. It is particulary well
suited for use in high-density and low power
system applications. This device has a data
retention mode that guarantees data to remain
valid at the minimum power supply voltage of
2.0V.
Product
Voltage Speed Operation
No. (V) (ns) Current(mA)
HY628400
5.0 55/70/85
10
Note 1. Normal : Normal Temperature
2. Current value are max.
FEATURES
• Fully static operation and Tri-state outputs
• TTL compatible inputs and outputs
• Low power consumption
• Battery backup(L/LL-part)
- 2.0V(min) data retention
• Standard pin configuration
- 32pin 525mil SOP
- 32pin 400mil TSOP-II
(Standard and Reversed)
Standby Current(uA)
L LL
100 30
Temperature
(°C)
0~70(Normal)
PIN CONNECTION
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SOP
32 Vcc A18 1
31
30
29
A15
A17
/WE
A16
A14
A12
2
3
4
28 A13
A7 5
27 A8
A6 6
26
25
A9
A11
24 /OE
A5 7
A4 8
A3 9
23
22
21
20
A10
/CS
I/O8
I/O7
A2
A1
A0
I/O1
10
11
12
13
19 I/O6 I/O2 14
18
17
I/O5 I/O3
I/O4 Vss
15
16
32 Vcc Vcc 32
31 A15 A15 31
30 A17 A17 30
29 /WE /WE 29
28 A13 A13 28
27 A8
A8 27
26
25
24
A9
A11
/OE
A9
A11
/OE
26
25
24
23
22
A10
/CS
A10
/CS
23
22
21
20
I/O8 I/O8
I/O7 I/O7
21
20
19 I/O6 I/O6 19
18 I/O5 I/O5 18
17 I/O4 I/O4 17
1
2
3
4
A18
A16
A14
A12
5 A7
6
7
A6
A5
8 A4
9 A3
10 A2
11
12
A1
A0
13 I/O1
14 I/O2
15 I/O3
16 Vss
TSOP-II(Standard)
TSOP-II(Reversed)
PIN DESCRIPTION
Pin Name
/CS
/WE
/OE
A0 ~ A18
I/O1 ~ I/O8
Vcc
Vss
Pin Function
Chip Select
Write Enable
Output Enable
Address Input
Data Input/Output
Power(5.0V)
Ground
BLOCK DIAGRAM
A0 ROW DECODER
A18
/CS
/OE
/WE
MEMORY ARRAY
1024x4096
I/O1
I/O8
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev.04 /Jan.99
Hyundai Semiconductor
1 page  
HY628400 Series
TIMING DIAGRAM
READ CYCLE 1
ADDR
OE
CS
Data
Out
High-Z
tRC
tAA
tOE
tOLZ
tACS
tCLZ
tOH
tOHZ
tCHZ
Data Valid
Note(READ CYCLE):
1. tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are
not referenced to output voltage levels
2. At any given temperature and voltage condition, tCHZ max. is less than tCLZ min. both for a given
device and from device to device.
3. /WE is high for the read cycle.
READ CYCLE 2
ADDR
Data
Out
tAA
tOH
Previous Data
tRC
Data Valid
tOH
Note(READ CYCLE):
1. /WE is high for the read cycle.
2. Device is continuously selected /CS = VIL
3. /OE =VIL.
Rev.04/Jan99
5
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet HY628400LG.PDF ] | |
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