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PDF SST49LF040B Data sheet ( Hoja de datos )
| Número de pieza | SST49LF040B | |
| Descripción | 4 Mbit LPC Flash | |
| Fabricantes | Silicon Storage Technology | |
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4 Mbit LPC Flash
SST49LF040B
FEATURES:
SST49LF040B4Mb LPC Flash memory
Advance Information
• 4 Mbit SuperFlash Memory Array for Code or
Data Storage
– SST49LF040B: 512K x8 (4 Mbit)
• Conforms to Intel LPC Interface Specification
– Supports Single-Byte LPC Memory Cycle
• Flexible Erase Capability
– Uniform 4 KByte sectors
– Uniform 64 KByte overlay blocks
– Chip-Erase for PP Mode Only
• Single 3.0-3.6V Read and Write Operations
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption
– Active Read Current: 6 mA (typical)
– Standby Current: 10 µA (typical)
• Fast Sector-Erase/Byte-Program Operation
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 70 ms (typical)
– Byte-Program Time: 14 µs (typical)
– Chip Rewrite Time: 8 seconds (typical)
– Single-pulse Program or Erase
– Internal timing generation
• Two Operational Modes
– Low Pin Count (LPC) interface mode for
in-system operation
– Parallel Programming (PP) mode for fast
production programming
• LPC Interface Mode
– LPC bus interface supporting byte Read and
Write
– 33 MHz clock frequency operation
– WP# and TBL# pins provide hardware write
protection for entire chip and/or top Boot Block
– Block Locking Registers for individual block
Write-Lock and Lock-Down protection
– JEDEC Standard SDP Command Set
– Data# Polling and Toggle Bit for End-of-Write
detection
– 5 GPI pins for system design flexibility
– 4 ID pins for multi-chip selection
• Parallel Programming (PP) Mode
– 11-pin multiplexed address and 8-pin data
I/O interface
– Supports fast In-System or PROM programming
for manufacturing
• CMOS and PCI I/O Compatibility
• Packages Available
– 32-lead PLCC
– 32-lead TSOP (8mm x 14mm)
• All non-Pb (lead-free) devices are RoHS compliant
PRODUCT DESCRIPTION
The SST49LF040B flash memory devices are designed to
interface with host controllers (chipsets) that support a low-
pin-count (LPC) interface for BIOS code storage. Two inter-
face modes are supported by the SST49LF040B: LPC
Memory mode for in-system operation compatible with
Intel’s LPC Interface Specification and Parallel Program-
ming (PP) mode to interface with industry-standard pro-
gramming equipment.
The SST49LF040B flash memory devices are manufac-
tured with SST’s proprietary, high-performance SuperFlash
technology. The split-gate cell design and thick-oxide tun-
neling injector attain greater reliability and manufacturability
compared with alternative approaches. The
SST49LF040B devices significantly improve performance
and reliability, while lowering power consumption. The
SST49LF040B devices write (Program or Erase) with a
single 3.0-3.6V power supply.
The SST49LF040B use less energy during Erase and Pro-
gram than alternative flash memory technologies. The total
energy consumed is a function of the applied voltage, cur-
rent and time of application. Since for any given voltage
range the SuperFlash technology uses less current to pro-
gram and has a shorter erase time, the total energy con-
sumed during any Erase or Program operation is less than
alternative flash memory technologies.
The SuperFlash technology provides fixed Erase and Pro-
gram times, independent of the number of Erase/Program
cycles that have occurred. This means the system software
or hardware does not have to be calibrated or correlated to
the cumulative number of Erase cycles as is necessary
with alternative flash memory technologies, whose Erase
and Program times increase with accumulated Erase/Pro-
gram cycles.
©2006 Silicon Storage Technology, Inc.
S71226-03-000
5/06
1
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
Intel is a registered trademark of Intel Corporation.
These specifications are subject to change without notice.
1 page  
4 Mbit LPC Flash
SST49LF040B
LIST OF TABLES
Advance Information
TABLE 1: Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
TABLE 2: Product Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
TABLE 3: LPC Memory Read Cycle Field Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
TABLE 4: LPC Memory Write Cycle Field Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
TABLE 5: LPC Memory Address Decoding Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
TABLE 6: LPC Memory Address bits definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
TABLE 7: LPC Memory Multiple Device Selection Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
TABLE 8: Block Locking Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
TABLE 9: Block Locking Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
TABLE 10: Operation Modes Selection (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
TABLE 11: Software Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
TABLE 12: DC Operating Characteristics (All Interfaces) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
TABLE 13: Recommended System Power-up Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
TABLE 14: Pin Capacitance (VDD=3.3V, TA=25 °C, f=1 Mhz, other pins open). . . . . . . . . . . . . . . . . . . . 22
TABLE 15: Reliability Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
TABLE 16: Clock Timing Parameters (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
TABLE 17: Read/Write Cycle Timing Parameters, VDD=3.0-3.6V (LPC Mode) . . . . . . . . . . . . . . . . . . . . . 24
TABLE 18: AC Input/Output Specifications (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
TABLE 19: Interface Measurement Condition Parameters (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . 26
TABLE 20: Reset Timing Parameters, VDD=3.0-3.6V (LPC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
TABLE 21: Reset Timing Parameters, VDD=3.0-3.6V (PP Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
TABLE 22: Read Cycle Timing Parameters, VDD=3.0-3.6V (PP Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . 28
TABLE 23: Program/Erase Cycle Timing Parameters, VDD=3.0-3.6V (PP Mode) . . . . . . . . . . . . . . . . . . . 28
TABLE 24: Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
©2006 Silicon Storage Technology, Inc.
5
S71226-03-000
5/06
5 Page 
4 Mbit LPC Flash
SST49LF040B
MODE SELECTION
The SST49LF040B flash memory device operates in two
distinct interface modes: the LPC mode and the Parallel
Programming (PP) mode. The MODE (Interface Mode
Select) pin is used to set the interface mode selection. If the
MODE pin is set to logic high, the device is in PP mode;
while if the MODE pin is set low, the device is in LPC mode.
The MODE selection pin must be configured prior to device
operation and must not change during operation. If the pin
is not connected, by default the Mode pin is internally
pulled low and the 49LF040B will be in LPC operation.
In LPC mode, communication between the Host and the
49LF040B occurs via the 4-bit I/O communication signals,
LAD[3:0] and LFRAME#. The 49LF040B detects the start
of an LPC cycle by reading the START field contents; a
0000b indicates the beginning of an LPC memory cycle.
In PP mode, the device is controlled via the 11 addresses,
A10-A0, and 8 I/O, DQ7-DQ0, signals. The address inputs
are multiplexed in row and column selected by control sig-
nal R/C# pin. The row addresses are mapped to the lower
internal addresses (A10-0), and the column addresses are
mapped to the higher internal addresses (A18-11). See Fig-
ure 4, Device Memory Map, for address assignments.
LPC MODE
Advance Information
Device Operation
The LPC mode uses a 5-signal communication interface
consisting of one control line, LFRAME#, which is driven by
the host to start or abort a bus cycle, and a 4-bit data bus,
LAD[3:0], which is used to communicate cycle type, cycle
direction, ID selection, address, data and sync fields. The
device enters standby mode when LFRAME# is high and
no internal operation is in progress.
The SST49LF040B supports single-byte LPC Memory
Read/Write cycles as defined in Intel’s Low-Pin-Count
Interface Specification. The host drives LFRAME# low for
one or more clock cycles to initiate an LPC cycle. The last
latched value of LAD[3:0] before LFRAME# is the START
value as defined in Tables 3 and 4 as well as Figures 5 and
6.
JEDEC standard SDP (Software Data Protection) Pro-
gram and Erase command sequences are used to initiate
LPC Memory Program and Erase operations. See Table
10 for a listing of Program and Erase commands. Chip-
Erase is only available in PP mode.
©2006 Silicon Storage Technology, Inc.
11
S71226-03-000
5/06
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SST49LF040B.PDF ] | |
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