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Si5341-40-RM 데이터시트 PDF




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Si5341-40-RM 데이터시트, 핀배열, 회로
U LTRA L OW J ITTER, A NY- F REQUENCY, A NY- O UTPUT
CLOCK GENERATOR
Si5341, Si5340
FAMILY REFERENCE MANUAL
Rev. 1.1 9/15
Copyright © 2015 by Silicon Laboratories
Si5341-40-RM




Si5341-40-RM pdf, 반도체, 판매, 대치품
Si5341-40-RM
LIST OF FIGURES
Figure 1. Block Diagram Si5341/40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 2. Si5341 Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 3. Si5340 Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 4. Power-Up and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 5. Crystal Resonator and External Reference Clock Connection Options . . . . . . . . . . 14
Figure 6. Terminations for Differential and Single-Ended Inputs. . . . . . . . . . . . . . . . . . . . . . . 15
Figure 7. LOS and LOL Fault Monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 8. Interrupt Flags and Masks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 9. Supported Differential Output Terminations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 10. LVCMOS Output Terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 11. Output Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 12. Example of Independently Configurable Path Delays . . . . . . . . . . . . . . . . . . . . . . 29
Figure 13. I2C/SPI Device Connectivity Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 14. I2C Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 15. 7-bit I2C Slave Address Bit-Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 16. I2C Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 17. I2C Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 18. SPI Interface Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 19. Example Writing Three Data Bytes using the Write Commands . . . . . . . . . . . . . . 38
Figure 20. Example of Reading Three Data Bytes Using the Read Commands. . . . . . . . . . . 38
Figure 21. SPI “Set Address” Command Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 22. SPI “Write Data” and “Write Data+ Address Increment” Instruction Timing . . . . . . 39
Figure 23. SPI “Read Data” and “Read Data + Address Increment” Instruction Timing . . . . . 40
Figure 24. SPI “Burst Data Write” Instruction Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 25. R1 (ESR) vs. C0 for 48 to 54 MHz Crystals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 26. R1 (ESR) vs. C0 for 25 MHz Crystals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 27. 64-pin Si5341 Crystal Layout Recommendations Top Layer (Layer 1) . . . . . . . . . 47
Figure 28. Zoom View Crystal Shield Layer, Below the Top Layer (Layer 2) . . . . . . . . . . . . . 47
Figure 29. Crystal Ground Plane (Layer 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 30. Power Plane (Layer 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 31. Layer 5 Power Routing on Power Plane (Layer 5). . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 32. Ground Plane (Layer 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 33. Output Clock Layer (Layer 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 34. Bottom Layer Ground Flooded (Layer 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 35. Device Layer (Layer 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 36. Crystal Shield Layer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 37. Ground Plane (Layer 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 38. Power Plane and Clock Output Power Supply Traces (Layer 4) . . . . . . . . . . . . . . 53
Figure 39. Clock Input Traces (Layer 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 40. Low-Speed CMOS Control and Status Signal Layer 6 (Bottom Layer) . . . . . . . . . 54
4 Rev. 1.1

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Si5341-40-RM 전자부품, 판매, 대치품
Si5341-40-RM
IN_ SEL[1:0]
IN0
IN1
IN2
Si 5341/ 40
PLL
XA
XB
FB_IN
OSC
Multi
Synth
Multi
Synth
Multi
Synth
Multi
Synth
Multi
Synth
NVM
I2C/ SPI
Control/
Status
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
Figure 1. Block Diagram Si5341/40
1.3. Available Software Tools and Support
ClockBuilder Pro is a software tool that is used for the Si5341/40 family and other product families, capable of
configuring the timing chip in an intuitive friendly step by step process. The software abstracts the details from the
user to allow focus on the high level input and output configuration, making it intuitive to understand and configure
for the end application. The software walks the user through each step, with explanations about each configuration
step in the process to explain the different options available. The software will restrict the user from entering an
invalid combination of selections. The final configuration settings can be saved, written to a device or written to the
EVB and a custom part number can be created. ClockBuilder Pro integrates all the datasheets, application notes
and information that might be helpful in one environment. It is intended that customers will use the software tool for
the proper configuration of the device. Register map descriptions are given in the document should not be the only
source of information for programming the device. The complexity of the algorithms is embedded in the software
tool.
Rev. 1.1
7

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Si5341-40-RM

CLOCK GENERATOR

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