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Si5341 데이터시트 PDF




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부품번호 Si5341 기능
기능 CLOCK GENERATOR
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Si5341 데이터시트, 핀배열, 회로
Si5341/40
L OW- J ITTER, 1 0 - O UTPUT, A NY- F REQUENCY, A NY- O UTPUT
CLOCK GENERATOR
Features
Generates up to 10 independent
DCO mode with frequency steps as
output clocks
low as 0.001 ppb
Ultra-low jitter: <100 fs RMS typical Independent output clock supply pins:
MultiSynth™ technology enables any- 3.3 V, 2.5 V, or 1.8 V
frequency synthesis on any-output Built-in power supply filtering and
Highly configurable outputs
regulation
compatible with LVDS, LVPECL, CML, Status monitoring: LOS, LOL
LVCMOS, HCSL, or programmable Serial Interface: I2C or SPI (3-wire or
voltage
4-wire)
Input frequency range:
User programmable (2x) non-volatile
External crystal: 25, 48-54 MHz
OTP memory
Differential clock: 10 to 750 MHz
LVCMOS clock: 10 to 250 MHz
Output frequency range:
Differential: 100 Hz to 712.5 MHz
LVCMOS: 100 Hz to 250 MHz
Output-output skew: 20 ps typ
Adjustable output-output delay
Optional zero delay mode
Independent glitchless on-the-fly
output frequency changes
ClockBuilderTM Pro software utility
simplifies device configuration and
assigns customer part numbers
Si5341: 4 input, 10 output, compact
9x9 mm, 64 QFN
Si5340: 4 input, 4 output, compact
7x7 mm, 44 QFN
Temperature range: –40 to +85 °C
Pb-free, RoHS-6 compliant
Device Selector Guide
Grade
Si534xA
Si534xB
Si534xC
Si534xD
Max Output Frequency
712.5 MHz
350 MHz
712.5 MHz
350 MHz
Frequency Synthesis Mode
Integer + Fractional
Integer Only
Applications
9x9 mm
7x7 mm
Ordering Information
See Section 8.
Functional Block Diagram
Si5341/40
IN_SEL[1:0]
IN0 ÷INT
IN1 ÷INT
IN2 ÷INT
XA
XB
FB_IN
OSC
÷INT
PLL
Clock tree generation replacing XOs,
buffers, signal format translators
Any-frequency clock translation
Clocking for FPGAs, processors,
memory
Ethernet switches/routers
OTN framers/mappers/processors
Test equipment & instrumentation
Broadcast video
Description
The any-frequency, any-output Si5341/40 clock generators combine a wide-band PLL
with proprietary MultiSynth fractional synthesizer technology to offer a versatile and
high performance clock generator platform. This highly flexible architecture is capable
of synthesizing a wide range of integer and non-integer related frequencies up to
712.5 MHz on 10 differential clock outputs while delivering sub-100 fs rms phase jitter
performance with 0 ppm error. Each of the clock outputs can be assigned its own
format and output voltage enabling the Si5341/40 to replace multiple clock ICs and
oscillators with a single device making it a true “clock tree on a chip”.
The Si5341/40 can be quickly and easily configured using ClockBuilder Pro software.
Custom part numbers are automatically assigned using a ClockBuilder Pro for fast,
free, and easy factory pre-programming, or the Si5341/40 can be programmed in-
circuit via I2C and SPI serial interfaces.
Multi
Synth
Multi
Synth
Multi
Synth
Multi
Synth
Multi
Synth
NVM
I2C/SPI
Control/
Status
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
Rev. 1.0 7/15
Copyright © 2015 by Silicon Laboratories
Si5341/40




Si5341 pdf, 반도체, 판매, 대치품
Si5341/40
1. Typical Application Schematic
161.1328125
MHz
Buffer
2x 161.1328125 MHz
LVDS
Buffer
133.33 MHz
2x 133.33 MHz
1.8V LVCMOS
Level
Translator
125 MHz
Buffer
Delay Line
Buffer
25 MHz
Clock
Generator
XA
XB
200 MHz
2.5V LVCMOS
Level
Translator
“Traditional Discrete” Clock Tree
3x 125 MHz
LVPECL
4x 125 MHz
3.3V LVCMOS
One Si5341 replaces:
3x crystal oscillators (XO)
2x buffers
1x Clock Generator
2x level translators
1x delay line
25 MHz
XA
XB
Si5341
“Clock Tree
On-a-Chip”
1x 161.1328125 MHz
LVDS
1x 161.1328125 MHz
LVDS
2x 133.33 MHz
1.8V LVCMOS
1x 125 MHz
LVPECL
1x 125 MHz
LVPECL
1x 125 MHz
LVPECL
2x 125 MHz
3.3V LVCMOS
2x 125 MHz
3.3V LVCMOS
2x 200 MHz
2.5V LVCMOS
2x 200 MHz
2.5V LVCMOS
Figure 1. Using The Si5341 to Replace a Traditional Clock Tree
4 Rev. 1.0

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Si5341 전자부품, 판매, 대치품
Si5341/40
Table 3. Input Specifications
(VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min Typ
Max
Units
Differential or Single-Ended/LVCMOS — AC-Coupled (IN0/IN0, IN1/IN1, IN2/IN2, FB_IN/FB_IN)
Input Frequency Range
fIN
Differential
10 — 750
Single-ended/LVCMOS 10 — 250
Input Voltage Swing5
VIN Differential AC Coupled 100 — 1800
fin < 250 MHz
MHz
mVpp_se
Differential AC Coupled 225 — 1800 mVpp_se
250 MHz < fin < 750 MHz
Slew Rate1, 2
Single-ended AC Coupled 100 — 3600 mVpp_se
fin < 250 MHz
SR
400 —
V/µs
Duty Cycle
DC
40 —
60
%
Capacitance
CIN
DC-Coupled CMOS Input Buffer (IN0, IN1, IN2)4
Input Frequency
Input Voltage
fIN
VIL
Slew Rate1, 2
VIH
SR
—2
10 —
–0.2 —
0.49 —
400 —
250
0.33
pF
MHz
V
V
V/µs
Duty Cycle
DC
Clock Input
40 —
60
%
Minimum Pulse Width
PW
Pulse Input
1.6 —
ns
Input Resistance
RIN
—8
Differential or Single-Ended/LVCMOS Clock at XA/XB
Input Frequency Range
fIN Frequency range for best 48 — 200
output
jitter performance
k
MHz
10 — 200
MHz
Input Single-ended Voltage Swing VIN_SE
365 — 2000 mVpp_se
Notes:
1. Imposed for jitter performance.
2. Rise and fall times can be estimated using the following simplified equation: tr/tf80-20 = ((0.8 - 0.2) * VIN_Vpp_se) / SR.
3. VDDIO is determined by the IO_VDD_SEL bit. It is selectable as VDDA or VDD.
4. DC-coupled CMOS Input Buffer selection is not supported in ClockBuilder Pro for new designs. For single-ended
LVCMOS inputs to IN0,1,2 it is required to ac-couple into the differential input buffer.
5. Voltage swing is specified as single-ended mVpp.
 
6. Contact Silicon Labs Technical Support for more details.
Rev. 1.0
7

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