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PDF AP32113 Data sheet ( Hoja de datos )
| Número de pieza | AP32113 | |
| Descripción | Microcontrollers | |
| Fabricantes | Infineon | |
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Application Note, V1.0, Mar. 2007
AP32113
Connecting Memory to
TC1130 External Bus Unit
(EBU)
Microcontrollers
1 page  
AP32113
Connecting Memory to the TC1130 External Bus Unit
(EBU)
3.5.3
3.5.4
3.5.5
3.5.6
3.5.7
3.6
3.7
3.7.1
3.7.1.1
3.7.1.2
3.7.2
3.7.3
3.8
Column Access Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Mode Register set up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Bank & Page memory Masking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Burst Access & Operation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Latency settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Access SDRAM Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Register settings for various SDRAM Devices . . . . . . . . . . . . . . . . . . . . . 30
Registers Independent of Device Type . . . . . . . . . . . . . . . . . . . . . . . . . 30
EBUCON - EBU Configuration Register . . . . . . . . . . . . . . . . . . . . . . 30
BUSCONx - EBU Bus Configuration Register . . . . . . . . . . . . . . . . . . 30
HY57V651620 SDRAM 100MHz device . . . . . . . . . . . . . . . . . . . . . . . . 31
HYB39S256160-8 SDRAM 125MHz device. . . . . . . . . . . . . . . . . . . . . . 31
Example to Program the SDRAM device present on TC1130 Triboard . . 32
Application Note
5
V1.0, 2006-02
5 Page 
AP32113
Connecting Memory to the TC1130 External Bus Unit
(EBU)
Table 3
Configuration Register Definition
Bit Name Description Intel F AMD ST ST Functional
(Intel)
29BDD M58BW M58LW Description
DOC
Data Output Bit 9 Bit 9
Configuration
Bit 9
Bit 9
0 1 clock cycle
1 Data valid for 2
clock cycles
WC Wait
Bit 8 Bit 8 Bit 8 Bit 8 0 Normal wait
Configuration
1 Wait advance by 1
clock
BS Burst
Bit 7 Bit 7 Bit 7 Bit 7 0 Interleaved
Sequence
1 Sequential
CC Clock
Bit 6 Bit 6 Bit 6 Bit 6 0 Falling edge clock
Configuration
1 Rising edge clock
BW
Wrap Control n/a n/a
Bit 3 n/a
0 Wrapping Burst
1 No wrapping
BL2-0
Burst Length Bit
Bit [2:0] Bit [2:0] Bit [2:0] Number of words per
[2:0]
burst.
1) The definition is device dependent, details please refer to corresponding device data sheet.
For writing to configuration register of Burst Flash, different waveforms are required. The
following registers need to be set:
• BUSCON.AGEN = 000B, Asynchronous device type is selected.
• BUSCON.CTYPE may need to be set for multiplexed device configuration.
• BUSCON.PORTW need to be set according to external device port width.
• BUSAP.WAITWRC (write pulse width) and BUSAP.DATAC (data hold time) are set
according to corresponding definition in device data sheet.
Normally the definition of parameters in BUSAP are based on the number of LMB clock
cycles. So the following formula is applied in most cases:
The number of clock cycles = Specified value time / One clock cycle time
Note: If the result contains fractions, it is counted as a whole number.
For example, chip is running at 120MHz (8.33 ns/period), Intel 28F640K device is
connected. According to data sheet of Intel 28F640K, the WE# write pulse width low is
minimum 60ns. Based on the formula above, the number of clock cycles for write pulse
width is 60/8.33 = 8 clock cycles. So the following setting should be done:
• BUSCON.MULTMAP = 1xxxxxxB
• BUSCON.CMULT = 001B
• BUSAP.WAITWRC = 010B
Application Note
11
V1.0, 2006-02
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AP32113.PDF ] | |
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