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부품번호 | LPC812M101JDH16 기능 |
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기능 | 32-bit ARM Cortex-M0+ microcontroller | ||
제조업체 | NXP Semiconductors | ||
로고 | |||
전체 30 페이지수
LPC81xM
32-bit ARM Cortex-M0+ microcontroller; up to 16 kB flash and
4 kB SRAM
Rev. 4.4 — 23 June 2015
Product data sheet
1. General description
The LPC81xM are an ARM Cortex-M0+ based, low-cost 32-bit MCU family operating at
CPU frequencies of up to 30 MHz. The LPC81xM support up to 16 kB of flash memory
and 4 kB of SRAM.
The peripheral complement of the LPC81xM includes a CRC engine, one I2C-bus
interface, up to three USARTs, up to two SPI interfaces, one multi-rate timer, self wake-up
timer, and state-configurable timer, one comparator, function-configurable I/O ports
through a switch matrix, an input pattern match engine, and up to 18 general-purpose I/O
pins.
2. Features and benefits
System:
ARM Cortex-M0+ processor, running at frequencies of up to 30 MHz with
single-cycle multiplier and fast single-cycle I/O port.
ARM Cortex-M0+ built-in Nested Vectored Interrupt Controller (NVIC).
System tick timer.
Serial Wire Debug (SWD) and JTAG boundary scan modes supported.
Micro Trace Buffer (MTB) supported.
Memory:
Up to 16 kB on-chip flash programming memory with 64 Byte page write and erase.
Up to 4 kB SRAM.
ROM API support:
Boot loader.
USART drivers.
I2C drivers.
Power profiles.
Flash In-Application Programming (IAP) and In-System Programming (ISP).
Digital peripherals:
High-speed GPIO interface connected to the ARM Cortex-M0+ IO bus with up to 18
General-Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors,
programmable open-drain mode, input inverter, and glitch filter.
High-current source output driver (20 mA) on four pins.
High-current sink driver (20 mA) on two true open-drain pins.
GPIO interrupt generation capability with boolean pattern-matching feature on eight
GPIO inputs.
Switch matrix for flexible configuration of each I/O pin function.
NXP Semiconductors
LPC81xM
32-bit ARM Cortex-M0+ microcontroller
5. Marking
The LPC81xM devices typically have the following top-side marking:
LPC81x
xxxxx
xxxxxxxx
xxYWWxR[x]
The last two letters in the last line (field ‘xR’) identify the boot code version and device
revision.
Table 3. Device revision table
Revision identifier (xR)
‘1A’
‘2A’
’4C’
Revision description
Initial device revision with boot code version 13.1
Device revision with boot code version 13.2
Device revision with boot code version 13.4
Field ‘Y’ states the year the device was manufactured. Field ‘WW’ states the week the
device was manufactured during that year.
Remark: On the TSSOP16 package, the last line includes only the date code xxYWW.
LPC81XM
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4.4 — 23 June 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
4 of 77
4페이지 NXP Semiconductors
LPC81xM
32-bit ARM Cortex-M0+ microcontroller
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Fig 5. Pin configuration TSSOP20 package (LPC812M101JDH20)
terminal 1
index area
XSON16
PIO0_13 1
PIO0_12 2
RESET/PIO0_5 3
PIO0_4/WAKEUP/TRST 4
SWCLK/PIO0_3/TCK 5
SWDIO/PIO0_2/TMS 6
PIO0_11 7
PIO0_10 8
16 PIO0_0/ACMP_I1/TDO
15 PIO0_6/VDDCMP
14 PIO0_7
13 VSS
12 VDD
11 PIO0_8/XTALIN
10 PIO0_9/XTALOUT
9 PIO0_1/ACMP_I2/CLKIN/TDI
aaa-009570
Transparent top view
Fig 6. Pin configuration XSON16 package (LPC812M101JTB16)
LPC81XM
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4.4 — 23 June 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
7 of 77
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부품번호 | 상세설명 및 기능 | 제조사 |
LPC812M101JDH16 | 32-bit ARM Cortex-M0+ microcontroller | NXP Semiconductors |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |