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TC58NVG1S3HTAI0 데이터시트 PDF




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부품번호 TC58NVG1S3HTAI0 기능
기능 2 GBIT (256M x 8 BIT) CMOS NAND E2PROM
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TC58NVG1S3HTAI0 데이터시트, 핀배열, 회로
TC58NVG1S3HTAI0
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
2 GBIT (256M 8 BIT) CMOS NAND E2PROM
DESCRIPTION
The TC58NVG1S3HTAI0 is a single 3.3V 2 Gbit (2,281,701,376 bits) NAND Electrically Erasable and
Programmable Read-Only Memory (NAND E2PROM) organized as (2048 128) bytes 64 pages 2048blocks.
The device has two 2176-byte static registers which allow program and read data to be transferred between the
register and the memory cell array in 2176-byte increments. The Erase operation is implemented in a single block
unit (128 Kbytes 8 Kbytes: 2176 bytes 64 pages).
The TC58NVG1S3HTAI0 is a serial-type memory device which utilizes the I/O pins for both address and data
input/output as well as for command inputs. The Erase and Program operations are automatically executed making
the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still
cameras and other systems which require high-density non-volatile memory data storage.
FEATURES
Organization
Memory cell array
Register
Page size
Block size
x8
2176 128K 8
2176 8
2176 bytes
(128K 8K) bytes
Modes
Read, Reset, Auto Page Program, Auto Block Erase, Status Read, Page Copy,
Multi Page Program, Multi Block Erase, Multi Page Copy, Multi Page Read
Mode control
Serial input/output
Command control
Number of valid blocks
Min 2008 blocks
Max 2048 blocks
Power supply
VCC 2.7V to 3.6V
Access time
Cell array to register 25 s max
Serial Read Cycle
25 ns min (CL=50pF)
Program/Erase time
Auto Page Program
Auto Block Erase
300 s/page typ.
2.5 ms/block typ.
Operating current
Read (25 ns cycle)
Program (avg.)
Erase (avg.)
Standby
30 mA max.
30 mA max
30 mA max
50 A max
Package
TSOP I 48-P-1220-0.50 (Weight: 0.53 g typ.)
8 bit ECC for each 512Byte is required.
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TC58NVG1S3HTAI0 pdf, 반도체, 판매, 대치품
TC58NVG1S3HTAI0
VALID BLOCKS
SYMBOL
PARAMETER
MIN
TYP.
MAX
UNIT
NVB Number of Valid Blocks
2008
2048
Blocks
NOTE:
The device occasionally contains unusable blocks. Refer to Application Note (13) toward the end of this document.
The first block (Block 0) is guaranteed to be a valid block at the time of shipment.
The specification for the minimum number of valid blocks is applicable over lifetime
The number of valid blocks is on the basis of single plane operations, and this may be decreased with two plane
operations.
RECOMMENDED DC OPERATING CONDITIONS
SYMBOL
PARAMETER
MIN
TYP.
MAX
UNIT
VCC
Power Supply Voltage
2.7 3.6 V
VIH High Level input Voltage
Vcc x 0.8
VCC 0.3
V
VIL Low Level Input Voltage
0.3*
Vcc x 0.2
* 2 V (pulse width lower than 20 ns)
DC CHARACTERISTICS (Ta -40 to 85, VCC 2.7 to 3.6V)
SYMBOL
PARAMETER
IIL
ILO
ICCO1
ICCO2
ICCO3
ICCS
Input Leakage Current
Output Leakage Current
Serial Read Current
Programming Current
Erasing Current
Standby Current
CONDITION
VIN 0 V to VCC
VOUT 0 V to VCC
CE VIL, IOUT 0 mA, tcycle 25 ns
CE VCC 0.2 V, WP 0 V/VCC
MIN

TYP.

MAX
10
10
30
30
30
50
V
UNIT
A
A
mA
mA
mA
A
VOH
High Level Output Voltage IOH  0.1 mA
Vcc – 0.2
V
VOL Low Level Output Voltage IOL 0.1 mA
IOL
( RY /BY )
Output current of RY /BY
pin
VOL 0.2 V
  0.2 V
4 mA
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TC58NVG1S3HTAI0 전자부품, 판매, 대치품
TIMING DIAGRAMS
Latch Timing Diagram for Command/Address/Data
TC58NVG1S3HTAI0
CLE
ALE
CE
RE
Setup Time
Hold Time
WE
tDS tDH
I/O
: VIH or VIL
Command Input Cycle Timing Diagram
CLE
CE
WE
ALE
I/O
tCLS
tCS
tCLH
tCH
tWP
tALS
tALH
tDS tDH
: VIH or VIL
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부품번호상세설명 및 기능제조사
TC58NVG1S3HTAI0

2 GBIT (256M x 8 BIT) CMOS NAND E2PROM

Toshiba
Toshiba

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