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CH7516 데이터시트 PDF




Chrontel에서 제조한 전자 부품 CH7516은 전자 산업 및 응용 분야에서
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부품번호 CH7516 기능
기능 4 Lane DP to 4 Channel LVDS Monitor Controller
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CH7516 데이터시트, 핀배열, 회로
Chrontel
CH7516
Brief Datasheet
CH7516 4 Lane DP to 4 Channel LVDS Monitor Controller
FEATURES
GENERAL DESCRIPTION
Supports DisplayPort specification version 1.1a.
Support 4 Main Link Lanes at either 1.62Gb/s or
2.7Gb/s link rate
Supports input color depth 6/8/10-bit per pixel in RGB
format
Support VESA and CEA timing standards up to
QSXGA 2560x2048 @ 60Hz or 4Kx2K@24/30Hz for
2D, and Full HD 1920x1080 @120Hz for 3D(L/R eye
frame at 60Hz each), with 10 bit graphic color depth
Support HDCP Amendment for DisplayPort Rev. 1.1a
with external key storage
Support Single Port, Dual Port and Quad port LVDS
Chrontel’s CH7516 is a low-cost, low-power
semiconductor device that translates the DisplayPort
signal to the LVDS in form of RGB/YCbCr 4:4:4/YCbCr
4:2:2. This innovative DisplayPort receiver with
integrated 4 channel LVDS transmitters is specially
designed to target the All-In-One PC and the notebook
market segments. Leveraging the DisplayPort’s unique
source/sink “Link Training” routine, the CH7516 is
capable of instantly bring up the video display to the LCD
when the initialization process is completed between
CH7516 and the graphic chip.
output interface with 6/8/10-bit color depth up to
400MHz pixel rate
Support both OpenLDI (or JEIDA), SPWG (or VESA)
and non-JEITA (10-bit only) bit mapping for LVDS
application
Flexible LVDS output pins swapping
2 channel IIS/ S/PDIF audio output
Support Dynamic Backlight luminance Control by the
command through AUX channel, or through the
interface of PWM in/out and Backlight Brightness
Control (OSD display)
The CH7516 is designed to meet the DisplayPort
Specification version 1.1a. The 4 DisplayPort Main Link
Lanes receiver supports input with data rate running at
either 1.62Gb/s or 2.7Gb/s, and can accept digital RGB
signal for LVDS output up to QSXGA 2560x2048@60Hz
or 4Kx2K@24/30Hz. With advanced 3D processing
module integrated, The CH7516 can support up to
1920x1080@120Hz 3D display mode, with
programmable emitter control signal and 3D LCD panel’s
backlight control signal output.
Support PWM bypass through and on-chip PWM
generation (range 30~100%)
Support Panel selection function with external hardware
configuration
Initiated and controlled by firmware which is loaded
from External BOOT ROM automatically upon power
up.
BOOT ROM data updated through I2C bus or AUX
Channel
Support dynamic refresh rate (DDR) switching
Supports Enhanced Framing Mode
3 work modes: connect 27MHz crystal, inject 27MHz
or 14.318MHz clock
Programmable LCD panel power sequence
The Backlight Enable control and the PWM are the two
kinds of backlight control functions designed in the
CH7516 Panel power control module. The brightness
control commands sent through AUX Channel can be
dynamically translated by CH7516 and converted into
LCD backlight control signal. Alternatively, the
brightness control commands can be input from the PWM
in and GOIO pin of Backlight Brightness Control. The
CH7516 will save the last setting of brightness level into
the external BOOT ROM and restore it upon power up.
The CH7516 can dynamically adjust backlight brightness
according to video stream to save power consumption and
it supports OSD display in this way.
Hot Plug Detection
Support chip power down by GPIO pin
Support power management mechanism through AUX
Channel
EMI reduction capability for DP input and LVDS
output. Spread spectrum control is available for
transmitting LVDS signal
Achieve bit error rate <10-9 for raw transport data per
lane and symbol error rate <10-12 for control data
Low power consumption
Offered in a 128-pin TQFP package (14 x 14mm)
The CH7516 will immediately convert the DisplayPort
signal to LVDS output after DisplayPort Link Training is
completed. This feature can be achieved by loading the
panel’s EDID and the CH7516’s configuration settings in
the serial external BOOT ROM connected to the CH7516.
During system power-up and upon completion of the
DisplayPort Link Training through AUX Channel,
CH7516 will generate LVDS signal according to the
panel power-up timing sequencing stored in the external
BOOT ROM.
APPLICATION
An advanced Power Management Unit (PMU) is
incorporated in CH7516, which is specially designed to
reduce power consumption in normal operation.
209-1000-063 Rev 0.3
2013-1-25
1




CH7516 pdf, 반도체, 판매, 대치품
CHRONTEL
1.0 PIN-OUT
1.1 Package Diagram
CH7516
RB
RESERVED
VDDPLL
GNDPLL
VDDPLL
XO
XI
DVDD
DGND
REFCK
GPIO[0]
GPIO[1]
NC
NC
NC
NC
NC
NC
NC
NC
AVDD
AGND
LC3P
LC3N
LD19P
LD19N
LD18P
LD18N
LD17P
LD17N
LD16P
LD16N
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
CHRONTEL
CH7516
TQFP128
96 AUXP
95 AUXN
94 PSEL[2]
93 PSEL[1]
92 PSEL[0]
91 PWRDN
90 SCLK
89 WS
88 SDATA/SPDIF
87 MCLK
86 DGND
85 DVDD
84 GPIO[3]
83 GPIO[2]
82 NC
81 NC
80 NC
79 NC
78 NC
77 NC
76 NC
75 NC
74 AVDD
73 AGND
72 LD0N
71 LD0P
70 LD1N
69 LD1P
68 LD2N
67 LD2P
66 LD3N
65 LD3P
Figure 2: CH7516 128-Pin TQFP Pin Out
4
209-1000-063 Rev 0.3
2013-1-25

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CH7516 전자부품, 판매, 대치품
CHRONTEL
2.0 PACKAGE DIMENSIONS
96
97
A
B
65 65
64 64
AB
128
1
33
32
CD
33
32
CH7516
96
97
E
E
Exposed Die pad
128
1
F
G
H
K
I
J
Figure 3: 128 pin TQFP package (14 X 14 mm)
Table of Dimensions
No. of Leads
SYMBOL
128 (14 X 14 mm) A B C D E F G H I J
Milli- MIN 15.85 13.90 0.35 0.13 5.30 0.95 0.05 0.85 0.45 0.09
meters MAX 16.15 14.10 0.45 0.23 6.35 1.05 0.15 1.15 0.75 0.20
Notes:
Conforms to JEDEC standard JESD-30 MO-220.
K
209-1000-063 Rev 0.3
2013-1-25
7

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