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PDF NOIP1SN025KA Data sheet ( Hoja de datos )
| Número de pieza | NOIP1SN025KA | |
| Descripción | PYTHON 25K/16K/12K/10K Global Shutter CMOS Image Sensors | |
| Fabricantes | ON Semiconductor | |
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NOIP1SN025KA,
NOIP1SN016KA,
NOIP1SN012KA,
NOIP1SN010KA
PYTHON 25K/16K/12K/10K
Global Shutter CMOS Image
Sensors
www.onsemi.com
Features
• A Pin-compatible Family with Multiple Resolutions:
♦ 25K = 5120 x 5120 Active Pixels
♦ 16K = 4096 x 4096 Active Pixels
♦ 12K = 4096 x 3072 Active Pixels
♦ 10K = 3840 x 2896 Active Pixels
• 4.5 mm x 4.5 mm Low Noise Global Shutter Pixels with
In-pixel Correlated Double Sampling (CDS)
• APS−H Optical Format (32.6 mm Diagonal) for 25K
• Monochrome (SN), Color (SE) and NIR (FN)
• Random Programmable Region of Interest (ROI) Readout
• Pipelined and Triggered Global Shutter
• On-chip Fixed Pattern Noise (FPN) Correction
• 10-bit Analog-to-Digital Converter (ADC)
• 32 Low-voltage Differential Signaling (LVDS) High-speed
Serial Outputs
• Serial Peripheral Interface (SPI)
• High-speed: 80 Frames per Second (fps) at 25 Mpix
• 4.6 W Power Dissipation at Full Resolution, x32 LVDS
Mode
• Operational Range: −40°C to +85°C
• 355-pin mPGA Package
• These Devices are Pb−Free and are RoHS Compliant
Figure 1. PYTHON XK Photograph
Applications
• Machine Vision
• Motion Monitoring
• Intelligent Traffic Systems (ITS)
• Pick and Place Machines
• Inspection
• Metrology
Description
The PYTHON xK family of CMOS image sensors provide high resolution with very high bandwidth (up to 80 frame per
second readout for 25 megapixel readout) in a pin−compatible family of devices.
The high sensitivity 4.5 mm pixels support both pipelined and triggered global shutter readout modes. The sensor also
supports correlated double sampling (CDS) readout in global shutter mode, reducing noise and increasing dynamic range.
The sensor is programmed using a four−wire serial peripheral interface. Black level can be calibrated automatically, or
adjusted using a user programmable offset. The sensor also supports readout of up to 32 separate regions of interest (ROI) to
increase frame rate. Image data is accessed through 32, 16, 8, or 4 LVDS channels, each running at 720 Mbps, and a separate
synchronization channel is provided to facilitate image reconstruction.
The PYTHON xK family is packaged in a 355-pin mPGA package and is available in a monochrome, Bayer color, and
extended near−infrared (NIR) configurations.
© Semiconductor Components Industries, LLC, 2015
September, 2015 − Rev. 0
1
Publication Order Number:
NOIP1SN025KA/D
1 page  
NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
Table 5. ELECTRICAL SPECIFICATIONS
Boldface Limits apply for TJ = TMIN to TMAX, all other limits TJ = +30°C (Notes 6, 7, 8 and 9)
Parameter
Description
Min
Typ Max Units
vdd_calib
Pixel calibration supply
4.2 V
gnd_calib
Pixel calibration ground. Not connected to substrate
0V
vdd_sel
Pixel select supply
4.2 V
gnd_sel
Pixel select ground. Not connected to substrate.
0 0 0V
vdd_casc
Cascode supply
vref_colmux [9] Column multiplexer reference supply
1.0 V
1.0 V
gnd_colbias
Column biasing ground. Dedicated ground signal for pixel biasing.
Connected to substrate
0V
gnd_colpc
Column precharge ground. Dedicated ground signal for pixel biasing.
Not connected to substrate
0
V
Ptot Total power consumption
4600
mW
Popt
Power consumption at lower pixel rates
Configurable
I/O - LVDS (EIA/TIA-644): Conforming to standard/additional specifications and deviations listed
fserdata
Data rate on data channels
DDR signaling - 32 data channels, 1 synchronization channel
720 Mbps
fserclock
Clock rate of output clock
Clock output for mesochronous signaling
360 MHz
Vicm
LVDS input common mode level
0.3 1.25 2.2 V
Tccsk
Channel to channel skew (training pattern allows per-channel skew
correction)
50 ps
LVDS Electrical/Interface
fin Input clock rate
360 MHz
tidc Input clock duty cycle
45 50 55 %
tj Input clock jitter
20 ps
fspi SPI clock rate
10 MHz
ratspi
10-bit (32 LVDS channels): ratio: fin/fspi
30
10-bit (16 LVDS channels): ratio: fin/fspi
60
10-bit (8 LVDS channels): ratio: fin/fspi
120
10-bit (4 LVDS channels): ratio: fin/fspi
240
6. All parameters are characterized for DC conditions after thermal equilibrium is established.
7. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is recommended
that normal precautions be taken to avoid application of any voltages higher than the maximum rated voltages to this high−impedance
circuit.
8. Minimum and maximum limits are guaranteed through test and design.
9. Vref_colmux supply should be able to source and sink current
www.onsemi.com
5
5 Page 
NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
OVERVIEW
Figure 9 gives an overview of the major functional blocks of the PYTHON sensor.
Image Core Bias
Image Core
Pixel Array
Control & Registers
LVDS Clock
Receiver
Column Structure
64 analog channels
Analog Front End (AFE)
64 x 10 bit
digital channels
Data Formatting
32 x 10 bit
digital channels
Serializers & LVDS Interface
Biasing &
Bandgap
External
Resistor
SPI Reset
Interface
32, 16, 8, 4 Multiplexed LVDS Output Channels
1 LVDS Channel
1 LVDS Clock Channel
Figure 9. Block Diagram
Image Core
The image core consists of:
• Pixel array
• Address decoders and row drivers
• Pixel biasing
The PYTHON 25MP pixel array contains 5120 (H) x
5120 (V) readable pixels with a pixel pitch of 4.5 mm.
The PYTHON 16MP/12MP/10MP image arrays contain
4224 (H) x 4112 (V) / 4224 (H) x 3088 (V) / 3968 (H) x
2912 (V) readable pixels, inclusive of 8 pixel rows and 64
pixel columns at every side to allow for reprocessing or color
reconstruction. The sensor uses in-pixel CDS architecture,
which makes it possible to achieve a low noise read out of
the pixel array in both global shutter shutter mode with CDS.
The function of the row drivers is to access the image array
to reset or read the pixel data. The row drivers are controlled
by the on-chip sequencer and can access the pixel array.
The pixel biasing block guarantees that the data on a pixel
is transferred properly to the column multiplexer when the
row drivers select a pixel line for readout.
LVDS Clock Receiver
The LVDS clock receiver receives an LVDS clock signal
and distributes the required clocks to the sensor.
Typical input clock frequency is 360 MHz. The clock
input needs to be terminated with a 100 W resistor.
Column Multiplexer
The 5120 pixels of one image row are stored in 5120
column sample-and-hold (S/H) stages. These stages store
both the reset and integrated signal levels.
The data stored in the column S/H stages is read out
through 64 parallel differential outputs operating at a
frequency of 36 MHz.
www.onsemi.com
11
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