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AVR200856 데이터시트 PDF




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기능 DDR2 SDRAM
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AVR200856 데이터시트, 핀배열, 회로
DDR2 SDRAM
AVR201628 (128M X 16 )
AVR200856 (256M X 8 )
AVR200412 (512M X 4 )
Features
VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V
JEDEC-standard 1.8V I/O (SSTL_18-compatible)
Differential data strobe (DQS, DQS#) option
4n-bit prefetch architecture
Duplicate output strobe (RDQS) option for x8
DLL to align DQ and DQS transitions with CK
8 internal banks for concurrent operation
Programmable CAS latency (CL)
Posted CAS additive latency (AL)
WRITE latency = READ latency - 1 tCK
Programmable burst lengths: 4 or 8
Adjustable data-output drive strength
64ms, 8192-cycle refresh
On-die termination (ODT)
Industrial temperature (IT) option
RoHS-compliant
Supports JEDEC clock jitter specification
Table 1: Key Timing Parameters
Options1
Marking
Configuration
512 Meg x 4 (64 Meg x 4 x 8 banks)
512M4
256 Meg x 8 (32 Meg x 8 x 8 banks)
256M8
128 Meg x 16 (16 Meg x 16 x 8 banks)
128M16
FBGA package (Pb-free) – x16
84-ball FBGA (11.5mm x 14mm) Rev. A
HG
FBGA package (Pb-free) – x4, x8
60-ball FBGA (11.5mm x 14mm) Rev. A
HG
Timing – cycle time
2.5ns @ CL = 6 (DDR2-800)
-25
3.0ns @ CL = 4 (DDR2-667)
-3E
3.0ns @ CL = 5 (DDR2-667)
-3
3.75ns @ CL = 4 (DDR2-533)
-37E
5.0ns @ CL = 3 (DDR2-400)
-5E
Self refresh
Standard
None
Operating temperature
Commercial (0°C TC 85°C)
Industrial (–40°C TC 95°C;
–40°C TA 85°C)
Revision
:A
None
IT
Note:
1. Not all options listed can be combined to
define an offered product. Use the Part
Catalog Search on www.micron.com for
product offerings and availability.
Speed Grade
-8G
-6F
-6G
-5F
-4D
CL = 3
400
400
400
400
400
Data Rate (MHz)
CL = 4
CL = 5
533 667
667 667
533 667
533 n/a
400 n/a
CL = 6
800
n/a
n/a
n/a
n/a
tRC (ns)
55
54
55
55
55




AVR200856 pdf, 반도체, 판매, 대치품
Functional Description
The DDR2 SDRAM uses a double data rate architecture to achieve high-speed opera-
tion. The double data rate architecture is essentially a 4n-prefetch architecture, with an
interface designed to transfer two data words per clock cycle at the I/O balls. A single
read or write access for the DDR2 SDRAM effectively consists of a single 4n-bit-wide, one-
clock-cycle data transfer at the internal DRAM core and four corresponding n-bit-wide,
one-half-clock-cycle data transfers at the I/O balls.
A bidirectional data strobe (DQS, DQS#) is transmitted externally, along with data, for
use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM
during READs and by the memory controller during WRITEs. DQS is edge-aligned with
data for READs and center-aligned with data for WRITEs. The x16 offering has two data
strobes, one for the lower byte (LDQS, LDQS#) and one for the upper byte (UDQS, UDQS#).
The DDR2 SDRAM operates from a differential clock (CK and CK#); the crossing of CK
going HIGH and CK# going LOW will be referred to as the positive edge of CK. Com-
mands (address and control signals) are registered at every positive edge of CK. Input
data is registered on both edges of DQS, and output data is referenced to both edges of
DQS as well as to both edges of CK.
Read and write accesses to the DDR2 SDRAM are burst-oriented; accesses start at a se-
lected location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVATE command, which is
then followed by a READ or WRITE command. The address bits registered coincident
with the ACTIVATE command are used to select the bank and row to be accessed. The
address bits registered coincident with the READ or WRITE command are used to select
the bank and the starting column location for the burst access.
The DDR2 SDRAM provides for programmable read or write burst lengths of four or
eight locations. DDR2 SDRAM supports interrupting a burst read of eight with another
read or a burst write of eight with another write. An auto precharge function may be
enabled to provide a self-timed row precharge that is initiated at the end of the burst
access.
As with standard DDR SDRAM, the pipelined, multibank architecture of DDR2 SDRAM
enables concurrent operation, thereby providing high, effective bandwidth by hiding
row precharge and activation time.
A self refresh mode is provided, along with a power-saving, power-down mode.
All inputs are compatible with the JEDEC standard for SSTL_18. All full drive-strength
outputs are SSTL_18-compatible.
Industrial Temperature
The industrial temperature (IT) option, if offered, has two simultaneous requirements:
ambient temperature surrounding the device cannot be less than –40°C or greater than
+85°C, and the case temperature cannot be less than –40°C or greater than +95°C. JE-
DEC specifications require the refresh rate to double when TC exceeds +85°C; this also
requires use of the high-temperature self refresh option. Additionally, ODT resistance
and the input/output impedance must be derated when TC is < 0°C or > +85°C.

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AVR200856 전자부품, 판매, 대치품
Figure 4: Functional Block Diagram – 256 Meg x 8
ODT
CKE
CK
CK#
CS#
RAS#
CAS#
WE#
Control
logic
Mode
registers
18
A0–A14,
BA0–BA2
18
Address
register
Refresh
counter
15
15
3
10
15
Row-
address
MUX
Bank 7
Bank 7
Bank 6
Bank 6
Bank 5
Bank 5
Bank 4
Bank 4
Bank 3
Bank 3
Bank 2
Bank 2
Bank 1
Bank 1
Bank 0
Bank 0
row-
address
latch
32,768
Memory array
(32,768 x 256 x 32)
and
decoder
Sense amplifers
8,192
32
2
Bank
control
logic
I/O gating
DM mask logic
256
(x32)
COL0, COL1
CK, CK#
8
32 Read
latch
8
8
8
MUX
8
Data
DLL
DRVRS
DQS 2
generator UDQS, UDQS#
Input LDQS, LDQS#
registers
22
Write
FIFO
32
and
drivers
2
42
Mask 2
8
2
22
2 RCVRS
8
Column-
address
counter/
latch
8
2
Column
decoder
CK,CK#
CK out
CK in
32 8
Data 8
8
COL0, COL1
88
8
8
2
ODT control VddQ
sw1 sw2 sw3
sw1 sw2 sw3
R1 R2 R3
R1 R2 R3
DQ0–DQ7
sw1 sw2 sw3
R1 R2 R3
R1 R2 R3
sw1 sw2 sw3
R1 R2 R3
R1 R2 R3
DQS, DQS#
RDQS#
RDQS
DM
VssQ

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AVR200856

DDR2 SDRAM

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