|
|
PDF AVR200412 Data sheet ( Hoja de datos )
| Número de pieza | AVR200412 | |
| Descripción | DDR2 SDRAM | |
| Fabricantes | A-LINK | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de AVR200412 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
DDR2 SDRAM
AVR201628 (128M X 16 )
AVR200856 (256M X 8 )
AVR200412 (512M X 4 )
Features
• VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V
• JEDEC-standard 1.8V I/O (SSTL_18-compatible)
• Differential data strobe (DQS, DQS#) option
• 4n-bit prefetch architecture
• Duplicate output strobe (RDQS) option for x8
• DLL to align DQ and DQS transitions with CK
• 8 internal banks for concurrent operation
• Programmable CAS latency (CL)
• Posted CAS additive latency (AL)
• WRITE latency = READ latency - 1 tCK
• Programmable burst lengths: 4 or 8
• Adjustable data-output drive strength
• 64ms, 8192-cycle refresh
• On-die termination (ODT)
• Industrial temperature (IT) option
• RoHS-compliant
• Supports JEDEC clock jitter specification
Table 1: Key Timing Parameters
Options1
Marking
• Configuration
– 512 Meg x 4 (64 Meg x 4 x 8 banks)
512M4
– 256 Meg x 8 (32 Meg x 8 x 8 banks)
256M8
– 128 Meg x 16 (16 Meg x 16 x 8 banks)
128M16
• FBGA package (Pb-free) – x16
– 84-ball FBGA (11.5mm x 14mm) Rev. A
HG
• FBGA package (Pb-free) – x4, x8
– 60-ball FBGA (11.5mm x 14mm) Rev. A
HG
• Timing – cycle time
– 2.5ns @ CL = 6 (DDR2-800)
-25
– 3.0ns @ CL = 4 (DDR2-667)
-3E
– 3.0ns @ CL = 5 (DDR2-667)
-3
– 3.75ns @ CL = 4 (DDR2-533)
-37E
– 5.0ns @ CL = 3 (DDR2-400)
-5E
• Self refresh
– Standard
None
• Operating temperature
– Commercial (0°C ≤ TC ≤ 85°C)
– Industrial (–40°C ≤ TC ≤ 95°C;
–40°C ≤ TA ≤ 85°C)
Revision
•
:A
None
IT
Note:
1. Not all options listed can be combined to
define an offered product. Use the Part
Catalog Search on www.micron.com for
product offerings and availability.
Speed Grade
-8G
-6F
-6G
-5F
-4D
CL = 3
400
400
400
400
400
Data Rate (MHz)
CL = 4
CL = 5
533 667
667 667
533 667
533 n/a
400 n/a
CL = 6
800
n/a
n/a
n/a
n/a
tRC (ns)
55
54
55
55
55
1 page  
Automotive Temperature
The automotive temperature (AT) option, if offered, has two simultaneous require-
ments: ambient temperature surrounding the device cannot be less than –40°C or
greater than +105°C, and the case temperature cannot be less than –40°C or greater
than +105°C. JEDEC specifications require the refresh rate to double when TC exceeds
+85°C; this also requires use of the high-temperature self refresh option. Additionally,
ODT resistance and the input/output impedance must be derated when TC is < 0°C or >
+85°C.
General Notes
• The functionality and the timing specifications discussed in this data sheet are for the
DLL-enabled mode of operation.
• Throughout the data sheet, the various figures and text refer to DQs as “DQ.” The DQ
term is to be interpreted as any and all DQ collectively, unless specifically stated oth-
erwise. Additionally, the x16 is divided into 2 bytes: the lower byte and the upper byte.
For the lower byte (DQ0–DQ7), DM refers to LDM and DQS refers to LDQS. For the
upper byte (DQ8–DQ15), DM refers to UDM and DQS refers to UDQS.
• Complete functionality is described throughout the document, and any page or dia-
gram may have been simplified to convey a topic and may not be inclusive of all
requirements.
• Any specific requirement takes precedence over a general statement.
5 Page 
Table 3: FBGA 84-Ball – x16 and 60-Ball – x4, x8 Descriptions
Symbol
A[13:0] (x16)
A[14:0] (x4, x8)
BA[2:0]
CK, CK#
CKE
CS#
LDM, UDM (DM)
ODT
RAS#, CAS#, WE#
DQ[15:0] (x16)
DQ[3:0] (x4)
DQ[7:0] (x8)
Type
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Description
Address inputs: Provide the row address for ACTIVE commands, and the column ad-
dress and auto precharge bit (A10) for READ/WRITE commands, to select one location out
of the memory array in the respective bank. A10 sampled during a PRECHARGE com-
mand determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected
by BA[2:0]) or all banks (A10 HIGH). The address inputs also provide the op-code during a
LOAD MODE command.
Bank address inputs: BA[2:0] define to which bank an ACTIVE, READ, WRITE, or PRE-
CHARGE command is being applied. BA[2:0] define which mode register, including MR,
EMR, EMR(2), and EMR(3), is loaded during the LOAD MODE command.
Clock: CK and CK# are differential clock inputs. All address and control input signals are
sampled on the crossing of the positive edge of CK and negative edge of CK#. Output
data (DQ and DQS/DQS#) is referenced to the crossings of CK and CK#.
Clock enable: CKE (registered HIGH) activates and CKE (registered LOW) deactivates
clocking circuitry on the DDR2 SDRAM. The specific circuitry that is enabled/disabled is
dependent on the DDR2 SDRAM configuration and operating mode. CKE LOW provides
precharge power-down and SELF REFRESH operation (all banks idle), or ACTIVATE power-
down (row active in any bank). CKE is synchronous for power-down entry, power-down
exit, output disable, and for self refresh entry. CKE is asynchronous for SELF REFRESH ex-
it. Input buffers (excluding CK, CK#, CKE, and ODT) are disabled during power-down.
Input buffers (excluding CKE) are disabled during self refresh. CKE is an SSTL_18 input
but will detect a LVCMOS LOW level once VDD is applied during first power-up. After VREF
has become stable during the power on and initialization sequence, it must be main-
tained for proper operation of the CKE receiver. For proper SELF REFRESH operation, VREF
must be maintained.
Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command
decoder. All commands are masked when CS# is registered high. CS# provides for exter-
nal bank selection on systems with multiple ranks. CS# is considered part of the com-
mand code.
Input data mask: DM is an input mask signal for write data. Input data is masked when
DM is concurrently sampled HIGH during a WRITE access. DM is sampled on both edges
of DQS. Although DM balls are input-only, the DM loading is designed to match that of
DQ and DQS balls. LDM is DM for lower byte DQ[7:0] and UDM is DM for upper byte
DQ[15:8].
On-die termination: ODT (registered HIGH) enables termination resistance internal to
the DDR2 SDRAM. When enabled, ODT is only applied to each of the following balls:
DQ[15:0], LDM, UDM, LDQS, LDQS#, UDQS, and UDQS# for the x16; DQ[7:0], DQS, DQS#,
RDQS, RDQS#, and DM for the x8; DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input
will be ignored if disabled via the LOAD MODE command.
Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being
entered.
Data input/output: Bidirectional data bus for 128 Meg x 16.
Bidirectional data bus for 512 Meg x 4.
Bidirectional data bus for 256 Meg x 8.
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AVR200412.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| AVR200412 | DDR2 SDRAM | A-LINK |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |