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PDF LTC2378-20 Data sheet ( Hoja de datos )
| Número de pieza | LTC2378-20 | |
| Descripción | Low Power SAR ADC | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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FEATURES
n 1Msps Throughput Rate
n ±0.5ppm INL (Typ)
n Guaranteed 20-Bit No Missing Codes
n Low Power: 21mW at 1Msps, 21µW at 1ksps
n 104dB SNR (Typ) at fIN = 2kHz
n –125dB THD (Typ) at fIN = 2kHz
n Digital Gain Compression (DGC)
n Guaranteed Operation to 85°C
n 2.5V Supply
n Fully Differential Input Range ±VREF
n VREF Input Range from 2.5V to 5.1V
n No Pipeline Delay, No Cycle Latency
n 1.8V to 5V I/O Voltages
n SPI-Compatible Serial I/O with Daisy-Chain Mode
n Internal Conversion Clock
n 16-Lead MSOP and 4mm × 3mm DFN Packages
APPLICATIONS
n Medical Imaging
n High Speed Data Acquisition
n Portable or Compact Instrumentation
n Industrial Process Control
n Low Power Battery-Operated Instrumentation
n ATE
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners. Patents Pending. Protected by U.S. Patents, including
7705765, 7961132, 8319673.
LTC2378-20
20-Bit, 1Msps, Low Power
SAR ADC with 0.5ppm INL
DESCRIPTION
The LTC®2378-20 is a low noise, low power, high speed
20-bit successive approximation register (SAR) ADC.
Operating from a 2.5V supply, the LTC2378-20 has a
±VREF fully differential input range with VREF ranging from
2.5V to 5.1V. The LTC2378-20 consumes only 21mW and
achieves ±2ppm INL maximum, no missing codes at 20
bits with 104dB SNR.
The LTC2378-20 has a high speed SPI-compatible serial
interface that supports 1.8V, 2.5V, 3.3V and 5V logic
while also featuring a daisy-chain mode. The fast 1Msps
throughput with no cycle latency makes the LTC2378-20
ideally suited for a wide variety of high speed applications.
An internal oscillator sets the conversion time, easing exter-
nal timing considerations. The LTC2378-20 automatically
powers down between conversions, leading to reduced
power dissipation that scales with the sampling rate.
The LTC2378-20 features a unique digital gain compres-
sion (DGC) function, which eliminates the driver amplifier’s
negative supply while preserving the full resolution of the
ADC. When enabled, the ADC performs a digital scaling
function that maps zero-scale code from 0V to 0.1 • VREF
and full-scale code from VREF to 0.9 • VREF. For a typical
reference voltage of 5V, the full-scale input range is now
0.5V to 4.5V, which provides adequate headroom for
powering the driving amplifier from a single 5.5V supply.
TYPICAL APPLICATION
2.5V 1.8V TO 5V
10µF
0.1µF
VREF
0V
VREF
0V
+
10Ω
6800pF
VDD OVDD CHAIN
IN+
RDL/SDI
SDO
3300pF
LTC2378-20
SCK
–
10Ω
IN–
6800pF
REF
BUSY
CNV
GND REF/DGC
2.5V TO 5.1V
237820 TA01
47µF
(X7R, 1210 SIZE)
SAMPLE CLOCK
VREF
For more information www.linear.com/LTC2378-20
Integral Nonlinearity vs Output Code
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0
262144 524288 786432 1048576
OUTPUT CODE
237820 TA02
237820fa
1
1 page  
LTC2378-20
A DC TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER
CONDITIONS
MIN TYP
MAX UNITS
tSCKH
tSCKL
tSSDISCK
tHSDISCK
SCK High Time
SCK Low Time
SDI Setup Time From SCK↑
SDI Hold Time From SCK↑
(Note 11)
(Note 11)
l4
l4
l4
l1
ns
ns
ns
ns
tSCKCH
tDSDO
tHSDO
SCK Period in Chain Mode
SDO Data Valid Delay from SCK↑
SDO Data Remains Valid Delay from SCK↑
tSCKCH = tSSDISCK + tDSDO (Note 11)
CCLL
=
=
20pF,
20pF,
OOVVDDDD
=
=
5.25V
2.5V
CL = 20pF, OVDD = 1.71V
CL = 20pF (Note 10)
l 13.5
l
l
l
l1
ns
7.5 ns
8 ns
9.5 ns
ns
tDSDOBUSYL SDO Data Valid Delay from BUSY↓
tEN Bus Enable Time After RDL↓
CL = 20pF (Note 10)
(Note 11)
l
l
5 ns
16 ns
tDIS Bus Relinquish Time After RDL↑
(Note 11)
l 13 ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may effect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground.
Note 3: When these pin voltages are taken below ground or above REF or
OVDD, they will be clamped by internal diodes. This product can handle
input currents up to 100mA below ground or above REF or OVDD without
latch-up.
Note 4: VDD = 2.5V, OVDD = 2.5V, REF = 5V, VCM = 2.5V, fSMPL = 1MHz,
REF/DGC = VREF.
Note 5: Recommended operating conditions.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: Bipolar zero-scale error is the offset voltage measured from
–0.5LSB when the output code flickers between 0000 0000 0000 0000 0000
and 1111 1111 1111 1111 1111. Full-scale bipolar error is the worst-case
of –FS or +FS untrimmed deviation from ideal first and last code transitions
and includes the effect of offset error.
Note 8: All specifications in dB are referred to a full-scale ±5V input with a
5V reference voltage.
Note 9: fSMPL = 1MHz, IREF varies proportionately with sample rate.
Note 10: Guaranteed by design, not subject to test.
Note 11: Parameter tested and guaranteed at OVDD = 1.71V, OVDD = 2.5V
and OVDD = 5.25V.
Note 12: tSCK of 10ns maximum allows a shift clock frequency up to
100MHz for rising capture.
0.8*OVDD
tDELAY
0.8*OVDD
0.2*OVDD
0.2*OVDD
tDELAY
0.8*OVDD
0.2*OVDD
50%
tWIDTH
Figure 1. Voltage Levels for Timing Specifications
50%
237820 F01
For more information www.linear.com/LTC2378-20
237820fa
5
5 Page 
LTC2378-20
APPLICATIONS INFORMATION
The ADC inputs may be modeled as a switched capacitor
load of the drive circuit. A drive circuit may rely partially
on attenuating switched-capacitor current spikes with
small filter capacitors CFILT placed directly at the ADC
inputs, and partially on the driver amplifier having suffi-
cient bandwidth to recover from the residual disturbance.
Amplifiers optimized for DC performance may not have
sufficient bandwidth to fully recover at the ADC’s maximum
conversion rate, which can produce nonlinearity and other
errors. Coupling filter circuits may be classified in three
broad categories:
Fully Settled – This case is characterized by filter time
constants and an overall settling time that is consider-
ably shorter than the sample period. When acquisition
begins, the coupling filter is disturbed. For a typical first
order RC filter, the disturbance will look like an initial step
with an exponential decay. The amplifier will have its own
response to the disturbance, which may include ringing. If
the input settles completely (to within the accuracy of the
LTC2378-20), the disturbance will not contribute any error.
Partially Settled – In this case, the beginning of acquisition
causes a disturbance of the coupling filter, which then
begins to settle out towards the nominal input voltage.
However, acquisition ends (and the conversion begins)
before the input settles to its final value. This generally
produces a gain error, but as long as the settling is linear,
no distortion is produced. The coupling filter’s response
is affected by the amplifier’s output impedance and other
parameters. A linear settling response to fast switched-
capacitor current spikes can NOT always be assumed for
precision, low bandwidth amplifiers. The coupling filter
serves to attenuate the current spikes’ high-frequency
energy before it reaches the amplifier.
Fully Averaged – If the coupling filter capacitors (CFILT) at the
ADC inputs are much larger than the ADC’s sample capacitors
(45pF), then the sampling glitch is greatly attenuated. The
driving amplifier effectively only sees the average sampling
current, which is quite small. At 1Msps, the equivalent input
resistance is approximately 22k (as shown in Figure 5), a
benign resistive load for most precision amplifiers. However,
resistive voltage division will occur between the coupling
filter’s DC resistance and the ADC’s equivalent (switched-
capacitor) input resistance, thus producing a gain error.
The input leakage currents of the LTC2378-20 should
also be considered when designing the input drive circuit,
because source impedances will convert input leakage
currents to an added input voltage error. The input leakage
currents, both common mode and differential, are typically
extremely small over the entire operating temperature
range. Figure 6 shows input leakage currents over tem-
perature for a typical part.
IN+ REQ LTC2378-20
CFILT >> 45pF
IN–
BIAS
VOLTAGE
CFILT >> 45pF
REQ
237820 F05
REQ
=
1
fSMPL • 45pF
Figure 5. Equivalent Circuit for the Differential Analog
Input of the LTC2378-20 at 1Msps
30
20
10
DIFFERENTIAL
0 COMMON
–10
–55 –35 –15 5 25 45
TEMPERATURE (°C)
65 85
237820 F06
Figure 6. Common Mode and Differential Input Leakage Current
over Temperature
Let RS1 and RS2 be the source impedances of the dif-
ferential input drive circuit shown in Figure 7, and let IL1
and IL2 be the leakage currents flowing out of the ADC’s
analog inputs. The voltage error, VE, due to the leakage
currents can be expressed as:
( )( )
VE
=
RS1
+RS2
2
•
IL1 –IL2
+
RS1 –RS2
•
IL1
+IL
2
2
The common mode input leakage current, (IL1 + IL2)/2, is
typically extremely small (Figure 6) over the entire operat-
For more information www.linear.com/LTC2378-20
237820fa
11
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet LTC2378-20.PDF ] | |
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