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PDF LTC2377-20 Data sheet ( Hoja de datos )
| Número de pieza | LTC2377-20 | |
| Descripción | Low Power SAR ADC | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de LTC2377-20 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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FEATURES
nn 500ksps Throughput Rate
nn ±0.5ppm INL (Typ)
nn Guaranteed 20-Bit No Missing Codes
nn Low Power: 10.5mW at 500ksps, 10.5µW at 500sps
nn 104dB SNR (Typ) at fIN = 2kHz
nn –125dB THD (Typ) at fIN = 2kHz
nn Digital Gain Compression (DGC)
nn Guaranteed Operation to 85°C
nn 2.5V Supply
nn Fully Differential Input Range ±VREF
nn VREF Input Range from 2.5V to 5.1V
nn No Pipeline Delay, No Cycle Latency
nn 1.8V to 5V I/O Voltages
nn SPI-Compatible Serial I/O with Daisy-Chain Mode
nn Internal Conversion Clock
nn 16-Lead MSOP and 4mm × 3mm DFN Packages
APPLICATIONS
nn Medical Imaging
nn High Speed Data Acquisition
nn Portable or Compact Instrumentation
nn Industrial Process Control
nn Low Power Battery-Operated Instrumentation
nn ATE
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners. Patents Pending. Protected by U.S. Patents, including
7705765, 7961132, 8319673.
LTC2377-20
20-Bit, 500ksps, Low Power
SAR ADC with 0.5ppm INL
DESCRIPTION
The LTC®2377-20 is a low noise, low power, high speed
20-bit successive approximation register (SAR) ADC. Op-
erating from a 2.5V supply, the LTC2377-20 has a ±VREF
fully differential input range with VREF ranging from 2.5V
to 5.1V. The LTC2377-20 consumes only 10.5mW and
achieves ±2ppm INL maximum, no missing codes at 20
bits with 104dB SNR.
The LTC2377-20 has a high speed SPI-compatible serial
interface that supports 1.8V, 2.5V, 3.3V and 5V logic
while also featuring a daisy-chain mode. The fast 500ksps
throughput with no cycle latency makes the LTC2377-20
ideally suited for a wide variety of high speed applications.
An internal oscillator sets the conversion time, easing exter-
nal timing considerations. The LTC2377-20 automatically
powers down between conversions, leading to reduced
power dissipation that scales with the sampling rate.
The LTC2377-20 features a unique digital gain compres-
sion (DGC) function, which eliminates the driver amplifier’s
negative supply while preserving the full resolution of the
ADC. When enabled, the ADC performs a digital scaling
function that maps zero-scale code from 0V to 0.1 • VREF
and full-scale code from VREF to 0.9 • VREF. For a typical
reference voltage of 5V, the full-scale input range is now
0.5V to 4.5V, which provides adequate headroom for
powering the driving amplifier from a single 5.5V supply.
TYPICAL APPLICATION
2.5V 1.8V TO 5V
10µF
0.1µF
VREF
0V
VREF
0V
+
10Ω
6800pF
VDD OVDD CHAIN
IN+
RDL/SDI
SDO
3300pF
LTC2377-20
SCK
–
10Ω
IN–
6800pF
REF
BUSY
CNV
GND REF/DGC
2.5V TO 5.1V
237720 TA01
47µF
(X7R, 1210 SIZE)
SAMPLE CLOCK
VREF
For more information www.linear.com/LTC2377-20
Integral Nonlinearity vs Output Code
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0
262144 524288 786432 1048576
OUTPUT CODE
237720 TA02
237720fa
1
1 page  
LTC2377-20
A DC TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER
CONDITIONS
MIN TYP
MAX UNITS
tSCKH
tSCKL
tSSDISCK
tHSDISCK
SCK High Time
SCK Low Time
SDI Setup Time From SCK↑
SDI Hold Time From SCK↑
(Note 11)
(Note 11)
l4
l4
l4
l1
ns
ns
ns
ns
tSCKCH
tDSDO
tHSDO
SCK Period in Chain Mode
SDO Data Valid Delay from SCK↑
SDO Data Remains Valid Delay from SCK↑
tSCKCH = tSSDISCK + tDSDO (Note 11)
CCLL
=
=
20pF,
20pF,
OOVVDDDD
=
=
5.25V
2.5V
CL = 20pF, OVDD = 1.71V
CL = 20pF (Note 10)
l 13.5
l
l
l
l1
ns
7.5 ns
8 ns
9.5 ns
ns
tDSDOBUSYL SDO Data Valid Delay from BUSY↓
tEN Bus Enable Time After RDL↓
CL = 20pF (Note 10)
(Note 11)
l
l
5 ns
16 ns
tDIS Bus Relinquish Time After RDL↑
(Note 11)
l 13 ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may effect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground.
Note 3: When these pin voltages are taken below ground or above REF or
OVDD, they will be clamped by internal diodes. This product can handle
input currents up to 100mA below ground or above REF or OVDD without
latch-up.
Note 4: VDD = 2.5V, OVDD = 2.5V, REF = 5V, VCM = 2.5V, fSMPL = 500kHz,
REF/DGC = VREF.
Note 5: Recommended operating conditions.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: Bipolar zero-scale error is the offset voltage measured from
–0.5LSB when the output code flickers between 0000 0000 0000 0000 0000
and 1111 1111 1111 1111 1111. Full-scale bipolar error is the worst-case
of –FS or +FS untrimmed deviation from ideal first and last code transitions
and includes the effect of offset error.
Note 8: All specifications in dB are referred to a full-scale ±5V input with a
5V reference voltage.
Note 9: fSMPL = 500kHz, IREF varies proportionately with sample rate.
Note 10: Guaranteed by design, not subject to test.
Note 11: Parameter tested and guaranteed at OVDD = 1.71V, OVDD = 2.5V
and OVDD = 5.25V.
Note 12: tSCK of 10ns maximum allows a shift clock frequency up to
100MHz for rising capture.
0.8*OVDD
tDELAY
0.8*OVDD
0.2*OVDD
0.2*OVDD
tDELAY
0.8*OVDD
0.2*OVDD
50%
tWIDTH
Figure 1. Voltage Levels for Timing Specifications
50%
237720 F01
For more information www.linear.com/LTC2377-20
237720fa
5
5 Page 
LTC2377-20
APPLICATIONS INFORMATION
011...111
011...110
000...001
000...000
111...111
111...110
BIPOLAR
ZERO
100...001
100...000
FSR = +FS – –FS
1LSB = FSR/1048576 ≈ 1ppm
–FSR/2
–1 0V 1
LSB LSB
INPUT VOLTAGE (V)
FSR/2 – 1LSB
237720 F02
Figure 2. LTC2377-20 Transfer Function
shown in Figure 3. The diodes at the input provide ESD
protection. In the acquisition phase, each input sees ap-
proximately 45pF (CIN) from the sampling CDAC in series
with 40Ω (RON) from the on-resistance of the sampling
switch. Any unwanted signal that is common to both
inputs will be reduced by the common mode rejection of
the ADC. The inputs draw a current spike while charging
the CIN capacitors during acquisition. During conversion,
the analog inputs draw only a small leakage current.
INPUT DRIVE CIRCUITS
A low impedance source can directly drive the high imped-
ance inputs of the LTC2377-20 without gain error. A high
impedance source should be buffered to minimize settling
time during acquisition and to optimize ADC linearity. For best
performance, a buffer amplifier should be used to drive the
analog inputs of the LTC2377-20. The amplifier provides low
output impedance, which produces fast settling of the analog
REF
IN+
RON
40Ω
CIN
45pF
REF
IN–
RON
40Ω
CIN
45pF
BIAS
VOLTAGE
237720 F03
Figure 3. The Equivalent Circuit for the
Differential Analog Input of the LTC2377-20
signal during the acquisition phase. It also provides isolation
between the signal source and the ADC input currents.
Noise and Distortion
The noise and distortion of the buffer amplifier and signal
source must be considered since they add to the ADC noise
and distortion. Noisy input signals should be filtered prior
to the buffer amplifier input with an appropriate filter to
minimize noise. The simple 1-pole RC lowpass filter (LPF1)
shown in Figure 4 is sufficient for many applications.
A coupling filter network (LPF2) should be used between
LPF2
SINGLE-ENDED-
INPUT SIGNAL LPF1
500Ω
6800pF
10Ω
3300pF
6600pF
10Ω
SINGLE-ENDED- 6800pF
BW = 48kHz TO-DIFFERENTIAL
DRIVER
BW = 1.2MHz
Figure 4. Input Signal Chain
IN+
LTC2377-20
IN–
237720 F04
the buffer and ADC input to minimize disturbances reflected
into the buffer from sampling transients. Long RC time
constants at the analog inputs will slow down the settling
of the analog inputs. Therefore, LPF2 typically requires a
wider bandwidth than LPF1. This filter also helps minimize
the noise contribution from the buffer. A buffer amplifier
with a low noise density must be selected to minimize
degradation of the SNR.
High quality capacitors and resistors should be used in the
RC filters since these components can add distortion. NPO
and silver mica type dielectric capacitors have excellent
linearity. Carbon surface mount resistors can generate
distortion from self heating and from damage that may
occur during soldering. Metal film surface mount resistors
are much less susceptible to both problems.
Input Currents
One of the biggest challenges in coupling an amplifier to
the LTC2377-20 is in dealing with current spikes drawn
by the ADC inputs at the start of each acquisition phase.
The ADC inputs may be modeled as a switched capacitor
237720fa
For more information www.linear.com/LTC2377-20
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LTC2377-20.PDF ] | |
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