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PDF LTC2376-16 Data sheet ( Hoja de datos )
| Número de pieza | LTC2376-16 | |
| Descripción | Low Power SAR ADC | |
| Fabricantes | Linear Technology | |
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Features
n 250ksps Throughput Rate
n ±0.5LSB INL (Max)
n Guaranteed 16-Bit No Missing Codes
n Low Power: 3.4mW at 250ksps, 3.4µW at 250sps
n 97dB SNR (Typ) at fIN = 2kHz
n –125dB THD (Typ) at fIN = 2kHz
n Digital Gain Compression (DGC)
n Guaranteed Operation to 125°C
n 2.5V Supply
n Fully Differential Input Range ±VREF
n VREF Input Range from 2.5V to 5.1V
n No Pipeline Delay, No Cycle Latency
n 1.8V to 5V I/O Voltages
n SPI-Compatible Serial I/O with Daisy-Chain Mode
n Internal Conversion Clock
n 16-Lead MSOP and 4mm × 3mm DFN Packages
Applications
n Medical Imaging
n High Speed Data Acquisition
n Portable or Compact Instrumentation
n Industrial Process Control
n Low Power Battery-Operated Instrumentation
n ATE
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners.
LTC2376-16
16-Bit, 250ksps, Low Power
SAR ADC with 97dB SNR
Description
The LTC®2376-16 is a low noise, low power, high speed
16-bit successive approximation register (SAR) ADC.
Operating from a 2.5V supply, the LTC2376-16 has a
±VREF fully differential input range with VREF ranging from
2.5V to 5.1V. The LTC2376-16 consumes only 3.4mW and
achieves ±0.5LSB INL maximum, no missing codes at 16
bits with 97dB SNR.
The LTC2376-16 has a high speed SPI-compatible se-
rial interface that supports 1.8V, 2.5V, 3.3V and 5V logic
while also featuring a daisy-chain mode. The fast 250ksps
throughput with no cycle latency makes the LTC2376-16
ideally suited for a wide variety of high speed applications.
An internal oscillator sets the conversion time, easing exter-
nal timing considerations. The LTC2376-16 automatically
powers down between conversions, leading to reduced
power dissipation that scales with the sampling rate.
The LTC2376-16 features a unique digital gain compres-
sion (DGC) function, which eliminates the driver amplifier’s
negative supply while preserving the full resolution of the
ADC. When enabled, the ADC performs a digital scaling
function that maps zero-scale code from 0V to 0.1 • VREF
and full-scale code from VREF to 0.9 • VREF. For a typical
reference voltage of 5V, the full-scale input range is now
0.5V to 4.5V, which provides adequate headroom for
powering the driving amplifier from a single 5.5V supply.
Typical Application
2.5V 1.8V TO 5V
10µF
0.1µF
VREF
0V
VREF
0V
+
20Ω
6800pF
VDD OVDD CHAIN
IN+
RDL/SDI
SDO
3300pF
LTC2376-16
SCK
–
20Ω
IN–
6800pF
REF
BUSY
CNV
GND REF/DGC
2.5V TO 5.1V
237616 TA01
47µF
(X5R, 0805 SIZE)
SAMPLE CLOCK
VREF
32k Point FFT fS = 250ksps, fIN = 2kHz
0 SNR = 97.1dB
–20 THD = –125dB
SINAD = 97.1dB
–40 SFDR = 128dB
–60
–80
–100
–120
–140
–160
–180
0
25 50 75 100 125
FREQUENCY (kHz)
237616 TA02
237616f
1
1 page  
LTC2376-16
A DC timing characteristics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER
CONDITIONS
MIN TYP
MAX UNITS
tSCK
tSCKH
tSCKL
tSSDISCK
tHSDISCK
tSCKCH
SCK Period
SCK High Time
SCK Low Time
SDI Setup Time From SCK↑
SDI Hold Time From SCK↑
SCK Period in Chain Mode
(Notes 11, 12)
(Note 11)
(Note 11)
tSCKCH = tSSDISCK + tDSDO (Note 11)
l 10
l4
l4
l4
l1
l 13.5
ns
ns
ns
ns
ns
ns
tDSDO
tHSDO
SDO Data Valid Delay from SCK↑
SDO Data Remains Valid Delay from SCK↑
CL = 20pF (Note 11)
CL = 20pF (Note 10)
l
l1
9.5 ns
ns
tDSDOBUSYL
tEN
tDIS
SDO Data Valid Delay from BUSY↓
Bus Enable Time After RDL↓
Bus Relinquish Time After RDL↑
CL = 20pF (Note 10)
(Note 11)
(Note 11)
l
l
l
5 ns
16 ns
13 ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may effect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground.
Note 3: When these pin voltages are taken below ground or above REF or
OVDD, they will be clamped by internal diodes. This product can handle
input currents up to 100mA below ground or above REF or OVDD without
latch-up.
Note 4: VDD = 2.5V, OVDD = 2.5V, REF = 5V, VCM = 2.5V, fSMPL = 250kHz,
REF/DGC = VREF.
Note 5: Recommended operating conditions.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: Bipolar zero-scale error is the offset voltage measured from
–0.5LSB when the output code flickers between 0000 0000 0000 0000 and
1111 1111 1111 1111. Full-scale bipolar error is the worst-case of –FS
or +FS untrimmed deviation from ideal first and last code transitions and
includes the effect of offset error.
Note 8: All specifications in dB are referred to a full-scale ±5V input with a
5V reference voltage.
Note 9: fSMPL = 250kHz, IREF varies proportionately with sample rate.
Note 10: Guaranteed by design, not subject to test.
Note 11: Parameter tested and guaranteed at OVDD = 1.71V, OVDD = 2.5V
and OVDD = 5.25V.
Note 12: tSCK of 10ns maximum allows a shift clock frequency up to
100MHz for rising capture.
0.8*OVDD
tDELAY
0.8*OVDD
0.2*OVDD
0.2*OVDD
tDELAY
0.8*OVDD
0.2*OVDD
50%
tWIDTH
Figure 1. Voltage Levels for Timing Specifications
50%
237616 F01
237616f
5
5 Page 
LTC2376-16
Applications Information
INPUT DRIVE CIRCUITS
A low impedance source can directly drive the high im-
pedance inputs of the LTC2376-16 without gain error. A
high impedance source should be buffered to minimize
settling time during acquisition and to optimize the dis-
tortion performance of the ADC. Minimizing settling time
is important even for DC inputs, because the ADC inputs
draw a current spike when entering acquisition.
For best performance, a buffer amplifier should be used
to drive the analog inputs of the LTC2376-16. The ampli-
fier provides low output impedance, which produces fast
settling of the analog signal during the acquisition phase.
It also provides isolation between the signal source and
the current spike the ADC inputs draw.
Input Filtering
The noise and distortion of the buffer amplifier and signal
source must be considered since they add to the ADC noise
and distortion. Noisy input signals should be filtered prior
to the buffer amplifier input with an appropriate filter to
minimize noise. The simple 1-pole RC lowpass filter (LPF1)
shown in Figure 4 is sufficient for many applications.
LPF2
SINGLE-ENDED-
INPUT SIGNAL LPF1
500Ω
6800pF
20Ω
3300pF
6600pF
20Ω
SINGLE-ENDED- 6800pF
BW = 48kHz TO-DIFFERENTIAL
DRIVER
BW = 600kHz
Figure 4. Input Signal Chain
IN+
LTC2376-16
IN–
237616 F04
Another filter network consisting of LPF2 should be used
between the buffer and ADC input to both minimize the
noise contribution of the buffer and to help minimize distur-
bances reflected into the buffer from sampling transients.
Long RC time constants at the analog inputs will slow
down the settling of the analog inputs. Therefore, LPF2
requires a wider bandwidth than LPF1. A buffer amplifier
with a low noise density must be selected to minimize
degradation of the SNR.
High quality capacitors and resistors should be used in the
RC filters since these components can add distortion. NPO
and silver mica type dielectric capacitors have excellent
linearity. Carbon surface mount resistors can generate
distortion from self heating and from damage that may
occur during soldering. Metal film surface mount resistors
are much less susceptible to both problems.
Single-Ended-to-Differential Conversion
For single-ended input signals, a single-ended to differential
conversion circuit must be used to produce a differential
signal at the inputs of the LTC2376-16. The LT6350 ADC
driver is recommended for performing single-ended-to-
differential conversions. The LT6350 is flexible and may
be configured to convert single-ended signals of various
amplitudes to the ±5V differential input range of the
LTC2376-16. The LT6350 is also available in H-grade to
complement the extended temperature operation of the
LTC2376-16 up to 125°C.
Figure 5a shows the LT6350 being used to convert a 0V
to 5V single-ended input signal. In this case, the first
amplifier is configured as a unity gain buffer and the single-
ended input signal directly drives the high-impedance
input of the amplifier. As shown in the FFT of Figure 5b,
the LT6350 drives the LTC2376-16 to near full data sheet
performance.
The LT6350 can also be used to buffer and convert large
true bipolar signals which swing below ground to the
±5V differential input range of the LTC2376-16 in order
to maximize the signal swing that can be digitized. Fig-
ure 6a shows the LT6350 being used to convert a ±10V
true bipolar signal for use by the LTC2376-16. In this
case, the first amplifier in the LT6350 is configured as
an inverting amplifier stage, which acts to attenuate and
level shift the input signal to the 0V to 5V input range of
the LTC2376-16. In the inverting amplifier configuration,
the single-ended input signal source no longer directly
drives a high impedance input of the first amplifier. The
input impedance is instead set by resistor RIN. RIN must
be chosen carefully based on the source impedance of the
signal source. Higher values of RIN tend to degrade both
the noise and distortion of the LT6350 and LTC2376-16
as a system.
237616f
11
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet LTC2376-16.PDF ] | |
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