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PDF CYRF89435 Data sheet ( Hoja de datos )
| Número de pieza | CYRF89435 | |
| Descripción | PRoC - CapSense | |
| Fabricantes | Cypress Semiconductor | |
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CYRF89435
PRoC™ - CapSense®
PRoC™ - CapSense®
PRoC-CS Features
■ Single Device, Two functions
❐ 8-bit flash based CapSense controller MCU function and
2.4-GHz WirelessUSB™ NL radio transceiver function in a
single device
■ Wide operating range: 1.9 V to 3.6 V
❐ Configurable capacitive sensing elements
❐ 7 μA per sensor at 500 ms scan rate
❐ Supports SmartSense™ Auto-tuning
❐ Supports a combination of CapSense® buttons, sliders, and
proximity sensors
❐ SmartSense_EMC offers superior noise immunity for
applications with challenging conducted and radiated noise
conditions
■ RF Attributes
❐ 2.4-GHz WirelessUSB-NL Transceiver function
❐ Operates in the 2.4-GHz ISM Band (2.402 GHz - 2.479 GHz)
❐ 1-Mbps over-the-air data rate
❐ Receive sensitivity typical: –87 dBm
❐ 1 μA typical current consumption in sleep state
❐ Closed-loop frequency synthesis
❐ Supports frequency-hopping spread spectrum
❐ On-chip packet framer with 64-byte first in first out (FIFO)
data buffer
❐ Built-in auto-retry-acknowledge protocol simplifies usage
❐ Built-in cyclic redundancy check (CRC), forward error
correction (FEC), data whitening
❐ Additional outputs for interrupt request (IRQ) generation
❐ Digital readout of received signal strength indication (RSSI)
■ MCU Attributes
❐ Powerful Harvard-architecture processor
❐ M8C CPU – Up to 4 MIPS with 24 MHz Internal clock, external
crystal resonator or clock signal
❐ Low power at high speed
■ Temperature range: 0 °C to +70 °C
■ Flexible on-chip memory
• 32 KB Flash/2 KB SRAM
❐ 50,000 flash erase/write cycles
❐ Partial flash updates
❐ Flexible protection modes
❐ In-system serial programming (ISSP)
■ Precision, programmable clocking
❐ Internal main oscillator (IMO): 6/12/24 MHz ± 5%
❐ Internal low-speed oscillator (ILO) at 32 kHz for watchdog
and sleep timers
❐ Precision 32 kHz oscillator for optional external crystal
■ Programmable pin configurations
❐ Up to 13 general-purpose I/Os (GPIOs)
❐ Dual mode GPIO: All GPIOs support digital I/O and analog
inputs
❐ 25-mA sink current on each GPIO
• 120 mA total sink current on all GPIOs
❐ Pull-up, high Z, open-drain modes on all GPIOs
❐ CMOS drive mode –5 mA source current on ports 0 and 1
and 1 mA on port 2
❐ 20 mA total source current on all GPIOs
■ Versatile analog system
❐ Low-dropout voltage regulator for all analog resources
❐ Common internal analog bus enabling capacitive sensing on
all pins
❐ High power supply rejection ratio (PSRR) comparator
❐ 8 to 10-bit incremental analog-to-digital converter (ADC)
■ Additional system resources
❐ I2C slave:
• Selectable to 50 kHz, 100 kHz, or 400 kHz
❐ SPI master and slave: Configurable 46.9 kHz to 12 MHz
❐ Three 16-bit timers
❐ Watchdog and sleep timers
❐ Integrated supervisory circuit
❐ Emulated E2PROM using flash memory
■ Complete development tools
❐ Free development tool (PSoC Designer™)
❐ Full-featured, in-circuit emulator (ICE) and programmer
❐ Full-speed emulation
❐ Complex breakpoint structure
❐ 128 KB trace memory
■ Package option
❐ 40-pin 6 mm × 6 mm QFN
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-76581 Rev. *F
• San Jose, CA 95134-1709 • 408-943-2600
Revised March 31, 2015
1 page  
CYRF89435
Analog Multiplexer System
The Analog Mux Bus can connect to every GPIO pin. Pins are
connected to the bus individually or in any combination. The bus
also connects to the analog system for analysis with the
CapSense block comparator.
Switch control logic enables selected pins to precharge
continuously under hardware control. This enables capacitive
measurement for applications such as touch sensing. Other
multiplexer applications include:
■ Complex capacitive sensing interfaces, such as sliders and
touchpads.
■ Chip-wide mux that allows analog input from any I/O pin.
■ Crosspoint connection between any I/O pin combinations.
WirelessUSB-NL System
WirelessUSB-NL, optimized to operate in the 2.4-GHz ISM band,
is Cypress's third generation of 2.4-GHz low-power RF
technology. WirelessUSB-NL implements a Gaussian
frequency-shift keying (GFSK) radio using a differentiated
single-mixer, closed-loop modulation design that optimizes
power efficiency and interference immunity. Closed-loop
modulation effectively eliminates the problem of frequency drift,
enabling WirelessUSB-NL to transmit up to 255-byte payloads
without repeatedly having to pay power penalties for re-locking
the phase-locked loop (PLL) as in open-loop designs
Among the advantages of WirelessUSB-NL are its fast lock times
and channel switching, along with the ability to transmit larger
payloads. Use of longer payload packets, compared to multiple
short payload packets, can reduce overhead, improve overall
power efficiency, and help alleviate spectrum crowding.
Combined with Cypress's Capacitive touch sense controllers,
WirelessUSB-NL also provides the lowest bill of materials (BOM)
cost solution for sophisticated PC peripheral applications such
as wireless keyboards and mice, as well as best-in-class
wireless performance in other demanding applications. such as
toys, remote controls, fitness, automation, presenter tools, and
gaming.
With PRoC-CS, the WirelessUSB-NL transceiver can add
wireless capability to a wide variety of CapSense applications.
The WirelessUSB-NL is a fully-integrated CMOS RF transceiver,
GFSK data modem, and packet framer, optimized for use in the
2.4-GHz ISM band. It contains transmit, receive, RF synthesizer,
and digital modem functions, with few external components. The
transmitter supports digital power control. The receiver uses
extensive digital processing for excellent overall performance,
even in the presence of interference and transmitter
impairments.
The product transmits GFSK data at approximately 0-dBm
output power. Sigma-Delta PLL delivers high-quality DC-coupled
transmit data path.
The low-IF receiver architecture produces good selectivity and
image rejection, with typical sensitivity of –87 dBm or better on
most channels. Sensitivity on channels that are integer multiples
of the crystal reference oscillator frequency (12 MHz) may show
approximately 5 dB degradation. Digital RSSI values are
available to monitor channel quality.
On-chip transmit and receive FIFO registers are available to
buffer the data transfer with MCU. Over-the-air data rate is
always 1 Mbps even when connected to a slow, low-cost MCU.
Built-in CRC, FEC, data whitening, and automatic
retry/acknowledge are all available to simplify and optimize
performance for individual applications.
For more details on the radio’s implementation details and timing
requriements, please go through the WirelessUSB-NL datasheet
in www.cypress.com.
Figure 2. WirelessUSB-NL logic Block Diagram
VIN VOUT
VDD1 ...VDD7
VDD_IO
PKT
LDO Linear
Regulator
GFSK
Modulator
PA
SPI_ SS
CLK
MISO
MOSI
Synthesizer VCO
ANT
ANTb
RST_n
Pwr/ Reset
BRCLK
Xtal Osc
XTALi XTALo
GFSK
Demodulator
GND GND
X
Image
Rej. Mxr.
LNA + BPF
Transmit Power Control
The following table lists recommended settings for register 9 for
short-range applications, where reduced transmit RF power is a
desirable trade off for lower current.
Table 1. Transmit Power Control
Power Setting
Description
Typical
Transmit
Power
(dBm)
Value of Register 9
Silicon ID Silicon ID
0x1002
0x2002
PA0 - Highest power
+1
0x1820
0x7820
PA2 - High power
0
0x1920
0x7920
PA4 - High power
–3
0x1A20
0x7A20
PA8 - Low power
–7.5
0x1C20
0x7C20
PA12 - Lower power –11.2
0x1E20
0x7E20
Note: Silicon ID can be read from Register 31.
Power-on and Register Initialization Sequence
For proper initialization at power up, VIN must ramp up at the
minimum overall ramp rate no slower than shown by TVIN
specification in the following figure. During this time, the RST_n
line must track the VIN voltage ramp-up profile to within
approximately 0.2 V. Since most MCU GPIO pins automatically
default to a high-Z condition at power up, it only requires a pull-up
resistor. When power is stable and the MCU POR releases, and
MCU begins to execute instructions, RST_n must then be pulsed
low as shown in Figure 13 on page 31, followed by writing Reg[27
= 0x4200. During or after this SPI transaction, the State Machine
status can be read to confirm FRAMER_ST= 1, indicating a
proper initialization.
Document Number: 001-76581 Rev. *F
Page 5 of 39
5 Page 
CYRF89435
Electrical Specifications – PSoC Core
This section presents the DC and AC electrical specifications of the CYRF89435 PSoC devices. For the latest electrical specifications,
confirm that you have the most recent datasheet by visiting the web at http://www.cypress.com/psoc.
Figure 4. Voltage versus CPU Frequency
3.6 V
1.9 V
750kHz
3 MHz
CPU Frequency
24 MHz
Absolute Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested.
Table 2. Absolute Maximum Ratings
Symbol
TSTG
VIN[3]
VIO
VIOZ[4]
IMIO
ESD
LU
Description
Conditions
Storage temperature
Higher storage temperatures reduce data
retention time. Recommended Storage
Temperature is +25 °C ± 25 °C. Extended
duration storage temperatures above 85 °C
degrades reliability.
–
DC input voltage
–
DC voltage applied to tristate
–
Maximum current into any port pin –
Electrostatic discharge voltage
Human body model ESD
i) RF pins (ANT, ANTb)
ii) Analog pins (XTALi, XTALo)
iii) Remaining pins
Latch-up current
In accordance with JESD78 standard
Min
–55
1.9
–0.5
–0.5
–25
500
500
2000
–
Operating Temperature
Table 3. Operating Temperature
Symbol
Description
TA Ambient temperature
–
Conditions
Min
0
Typ Max Units
25 125 °C
– 3.63 V
– VIN + 0.5 V
– VIN + 0.5 V
– +50 mA
–– V
– 140 mA
Typ Max Units
– 70 °C
Notes
3. Program the device at 3.3 V only. Hence use MiniProg3 only as MiniProg1 does not support programming at 3.3 V.
4. Port1 pins are hot-swap capable with I/O configured in High-Z mode, and pin input voltage above VIN.
Document Number: 001-76581 Rev. *F
Page 11 of 39
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