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PDF PCH7900 Data sheet ( Hoja de datos )
| Número de pieza | PCH7900 | |
| Descripción | Fractional-N Transmitter IC | |
| Fabricantes | NXP Semiconductors | |
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PCF7900
PCH7900
Fractional-N Transmitter IC (FraNTIC)
Product Specification
Confidential
2007 Dec 13
1 page  
NXP Semiconductors
Fractional-N Transmitter IC (FraNTIC)
Product Specification
PCF7900 / PCH7900
3 PACKAGE OUTLINE
HVQFN16: plastic thermal enhanced very thin quad flat package; no leads;
16 terminals; body 3 x 3 x 0.85 mm
terminal 1
index area
D BA
E
A
A1
detail X
SOT758-1
c
L
4
Eh
1
e
5
e1
1/2 e
b
8
vM C AB
wM C
9
e
e2
1/2 e
12
y1 C
C
y
terminal 1
16
13
index area
Dh
0 2.5
DIMENSIONS (mm are the original
)
UNIT
A(1)
max.
A1
b
c
D(1)
Dh
mm
1
0.05 0.30
0.00 0.18
0.2
3.1 1.75
2.9 1.45
E(1) Eh
3.1 1.75
2.9 1.45
scale
e e1
0.5 1.5
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
e2
1.5
OUTLINE
VERSION
SOT758-1
IEC
---
REFERENCES
JEDEC
JEITA
MO-220
---
5 mm
X
L v w y y1
0.5
0.3
0.1
0.05 0.05 0.1
EUROPEAN
PROJECTION
ISSUE DATE
02-03-25
02-10-21
Figure 1. Package Outline HVQFN16
2007 Dec 13 5 Confidential
5 Page 
NXP Semiconductors
Fractional-N Transmitter IC (FraNTIC)
After a transmit command the EN pin has an additional
function: At the falling edge of the EN pin the level of the
SDIO pin is latched and directly connected to the modulator
input. In this case it is possible to intercept the RF-data
transmission without deactivating the PA and to loop the
last transmitted bit while the SDIO interface is used for SFR
configuration. But notice, EN must not be low for more than
216 XTAL clocks otherwise the device will be reset.
SCK
SCK is the clock input for the serial interface. Depending
on the start-up condition of SCK at the rising edge of EN
(see 5.9.2) each rising/falling edge of SCK shifts data into
or gets data from the SPI register-set. During RF data
transmission SCK is don’t care (signal on SCK has no
influence on interface).
SDIO
SDIO is the configurable bi-directional data input/output pin
of the serial interface. By default, the bi-directional mode is
configured, so SDIO is used for both input and output data
transmission. If ENSDO in register ACON2 is set, SDIO is
used as input only and TEST1 is configured as data output
SDO (4 wire interface ) . The SDO pin is high ohmic until
data is written.
Table 2 serial data output / TEST1 control (ENSDO)
ENSDO
0
1
SDO/TEST1 control state
pin TEST1 not used (only for test purposes)
pin TEST1 used as SDO (serial data output)
Data In or Data Out operation is adapted automatically
during SPI communication sequences.
Command Overview:
EN
SCK
SDIO C1 C0 A B C D E F
Figure 7. Command Overview
DATA
C1 C0
00
01
10
11
Command
write SFR
read SFR
transmit
antenna tune
A-F
Start address A5..A0
Start address A5..A0
transmit options
transmit options
Product Specification
PCF7900 / PCH7900
5.2.3 Reference Oscillator
The reference oscillator is of Pierce type with automatic
amplitude regulation and gain control to reduce the total
current consumption. The device pins XTAL1 and XTAL2
connect the internal circuitry to the external reference
crystal resonator and the load capacitances. To get
oscillation on the specified crystal frequency the input
capacitances of the two XTAL pins and PCB parasitics
have to be considered. The oscillator typically operates at
frequencies ranging from 9 MHz to 19 MHz to achieve the
allowed transmit frequencies.
5.2.4 Baud Rate Generator
The output-pin of the integrated baud-rate generator,
CKOUT, will provide a clock, which is derived from the
XTAL clock frequency. The baud rate is programmable by
a special function register-set (BDSEL, SCSEL). CKOUT is
not always active. (see chapter 0)
5.2.5 Power Amplifier
The Power Amplifier is driven from the PLL synthesizer and
operates in single ended fashion, according to
Figure 11.
The Power Amplifier output (pin PAOUT) requires an
external DC path to pin VBAT, established by the antenna
loop or a dedicated bias coil. A dedicated ground pin
(VSSPA) is provided to improve the RF properties of the
circuitry. Pin VSSPA must be connected with pin VSS. Best
efficiency is achieved, if the output voltage swing at pin
PAOUT yields one volt less than two times the supply
voltage: VPAOUT PP ~ 2 (VVDDA – 0.5V).
Three special-function-registers ACON0, ACON1 and
ACON2 are available to control the output power of the 4
binary weighted output stages.
The Power Amplifier also features three regulated and one
unregulated (high power) output power modes, as selected
by the control bits PAM1 and PAM0 located in the TXCON
register. In regulated mode the input drive level of the
amplifier is derived from an internal reference voltage and
so the output power is stabilized against supply voltage
and temperature variations over a large degree.
2007 Dec 13 11 Confidential
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet PCH7900.PDF ] | |
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