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Número de pieza | NDD04N50Z | |
Descripción | N-Channel Power MOSFET / Transistor | |
Fabricantes | ON Semiconductor | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de NDD04N50Z (archivo pdf) en la parte inferior de esta página. Total 8 Páginas | ||
No Preview Available ! NDD04N50Z
N-Channel Power MOSFET
500 V, 2.7 W
Features
• Low ON Resistance
• Low Gate Charge
• ESD Diode−Protected Gate
• 100% Avalanche Tested
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
ABSOLUTE MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain−to−Source Voltage
Continuous Drain Current RqJC
Continuous Drain Current
RqJC, TA = 100°C
Pulsed Drain Current, VGS @ 10 V
Power Dissipation RqJC
Gate−to−Source Voltage
Single Pulse Avalanche Energy,
ID = 3.4 A
ESD (HBM) (JESD22−A114)
Peak Diode Recovery
VDSS
ID
ID
IDM
PD
VGS
EAS
Vesd
dv/dt
500
3.0
1.9
12
61
±30
120
2800
4.5 (Note 1)
V
A
A
A
W
V
mJ
V
V/ns
Continuous Source Current
(Body Diode)
IS 3.4 A
Maximum Temperature for Soldering
Leads
TL
260 °C
Operating Junction and
Storage Temperature Range
TJ, Tstg
−55 to 150
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. ID v 3.4 A, di/dt ≤ 200 A/ms, VDD ≤ BVDSS, TJ ≤ 150°C.
http://onsemi.com
VDSS
500 V
RDS(on) (MAX) @ 1.5 A
2.7 W
N−Channel
D (2)
G (1)
S (3)
4
4
1 23
IPAK
CASE 369D
STYLE 2
12
3
DPAK
CASE 369AA
STYLE 2
MARKING AND ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
© Semiconductor Components Industries, LLC, 2011
September, 2011 − Rev. 1
1
Publication Order Number:
NDD04N50Z/D
1 page NDD04N50Z
100
VGS v 30 V
SINGLE PULSE
10 TC = 25°C
1
100 ms 10 ms
1 ms
10 ms
dc
0.1
0.01
0.1
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
1 10 100 1000
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 12. Maximum Rated Forward Biased
Safe Operating Area NDD04N50Z
10
50% (DUTY CYCLE)
1
20%
10%
5.0%
0.1 2.0%
1.0%
SINGLE PULSE
0.01
1E−06
1E−05
1E−04
1E−03
1E−02
1E−01
PULSE TIME (s)
1E+00
1E+01
Figure 13. Thermal Impedance (Junction−to−Case) for NDD04N50Z
RqJA = 2°C/W
Steady State
1E+02
1E+03
100
10 50% (DUTY CYCLE)
20%
10%
1 5.0%
2.0%
1.0%
0.1
0.01
1E−06
SINGLE PULSE
1E−05
1E−04
1E−03
1E−02
1E−01
1E+00
1E+01
PULSE TIME (s)
Figure 14. Thermal Impedance (Junction−to−Ambient) for NDD04N50Z
RqJA = 40°C/W
Steady State
1E+02
1E+03
http://onsemi.com
5
5 Page |
Páginas | Total 8 Páginas | |
PDF Descargar | [ Datasheet NDD04N50Z.PDF ] |
Número de pieza | Descripción | Fabricantes |
NDD04N50Z | N-Channel Power MOSFET / Transistor | ON Semiconductor |
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