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PDF STP180NS04ZC Data sheet ( Hoja de datos )
| Número de pieza | STP180NS04ZC | |
| Descripción | N-channel Power MOSFET | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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STP180NS04ZC
N-channel 40 V clamped 3.6 mΩ typ., 120 A
fully protected SAFeFET™ Power MOSFET in a TO-220 package
Datasheet - production data
Features
TAB
3
2
1
TO-220
Order code
VDS
RDS(on) max ID
STP180NS04ZC 40 V clamped 4.2 mΩ 120 A
• Low capacitance and gate charge
• 100% avalanche tested
• 175 °C maximum junction temperature
Applications
• Switching and linear applications
Figure 1. Internal schematic diagram
D(2,TAB)
G(1)
Description
This fully clamped Power MOSFET is
manufactured using an advanced mesh overlay
process which is based on an innovative strip
layout. The benefits of this technology, coupled
with the extra clamping capabilities render this
device particularly suitable for the harshest
operating conditions, such as those associated
with the automotive environment. The device is
also suitable for other applications that require a
high degree of ruggedness.
S(3)
Order code
STP180NS04ZC
Table 1. Device summary
Marking
Package
P180NS04ZC
TO-220
Packaging
Tube
March 2013
This is information on a product in full production.
DocID14603 Rev 2
1/14
www.st.com
14
1 page  
STP180NS04ZC
2 Electrical characteristics
Electrical characteristics
(TCASE=25°C unless otherwise specified)
Symbol
Parameter
Table 5. On/off states
Test conditions
Min. Typ. Max. Unit
V(BR)DG Clamped voltage
ID = 1 mA, VGS = 0
33 41 V
-40 < Tj < 175 °C
Drain-source clamping
VDSR(CL) voltage (DC)
IGS(CL) = -2 mA, ID = 1 A
41 V
Zero gate voltage
IDSS
drain current (VGS = 0)
Gate-body leakage
(1)
IGSS
current (VDS = 0)
Gate-source
VGSS
breakdown voltage
VDS = 16 V
VDS = 16 V, Tj = 150 °C
VDS = 16 V, Tj = 175 °C
VGS = ±10 V
VGS = ±10 V,Tj = 175 °C
VGS = ±16 V,Tj = 175 °C
IGS = ±100 μA
18
1 μA
50 μA
100 μA
±2
±50
±150
μA
μA
μA
25 V
VGS(th) Gate threshold voltage
Static drain-source on-
RDS(on) resistance
VDS = VGS, ID = 1 mA
VGS = 10 V, ID = 40 A
234
3.6 4.2
RG Internal gate resistor
14
1. Gate Oxide, without zener diodes, tested at wafer sorting (IGSS < ± 100 nA @ ± 20 V Tj=25 °C).
Figure 17: Unclamped inductive load test circuit for electrical schematics
V
mΩ
Ω
Symbol
Parameter
Ciss
Coss
Crss
tr(Voff)
tf
tc
Qg
Qgs
Qgd
Input capacitance
Output capacitance
Reverse transfer
capacitance
Off voltage rise time
Fall time
Cross-over time
Total gate charge
Gate-source charge
Gate-drain charge
Table 6. Dynamic
Test conditions
Min. Typ. Max. Unit
VDS =25 V, f=1 MHz, VGS=0
- 4500
- 1700
- 500
-
-
-
pF
pF
pF
VCLAMP=30 V, ID=80 A,
VGS=10 V, RG=4.7 Ω
(see Figure 14)
VDD=20 V, ID = 120 A
VGS =10 V
(see Figure 15)
- 250 -
- 115 -
- 290 -
- 110 -
- 25 -
- 45 -
ns
ns
ns
nC
nC
nC
DocID14603 Rev 2
5/14
5 Page 
STP180NS04ZC
Dim.
A
b
b1
c
D
D1
E
e
e1
F
H1
J1
L
L1
L20
L30
∅P
Q
Package mechanical data
Table 8. TO-220 type A mechanical data
mm
Min.
Typ.
4.40
0.61
1.14
0.48
15.25
10
2.40
4.95
1.23
6.20
2.40
13
3.50
3.75
2.65
1.27
16.40
28.90
Max.
4.60
0.88
1.70
0.70
15.75
10.40
2.70
5.15
1.32
6.60
2.72
14
3.93
3.85
2.95
DocID14603 Rev 2
11/14
11 Page | ||
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| PDF Descargar | [ Datasheet STP180NS04ZC.PDF ] | |
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