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MAX11259 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 MAX11259
기능 Delta-Sigma ADC
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MAX11259 데이터시트, 핀배열, 회로
MAX11259
EVALUATION KIT AVAILABLE
24-Bit, 6-Channel, 16ksps, 6.2nV/√Hz PGA,
Delta-Sigma ADC with I2C Interface
General Description
The MAX11259 is a 6-channel, 24-bit delta-sigma ADC
that achieves exceptional performance while consuming
very low power. Sample rates up to 16ksps allow preci-
sion DC measurements. The MAX11259 communicates
via an I2C-compatible serial interface and is available in a
small (3mm x 3mm) WLP package.
The MAX11259 offers a 6.2nV/Hz noise programmable
gain amplifier (PGA) with gain settings from 1x to 128x.
The integrated PGA provides isolation of the signal inputs
from the switched capacitor sampling network. The PGA
also enables the MAX11259 to interface directly with
high-impedance sources without compromising available
dynamic range.
The MAX11259 operates from a single 2.7V to 3.6V
analog supply, or split ±1.8V analog supplies, allowing
the analog input to be sampled below ground. The digital
supply range is 1.7V to 2.0V or 2.0V to 3.6V, allowing
communication with 1.8V, 2.5V, 3V, or 3.3V logic.
Applications
● Wearable Electronics
● Weigh Scales
● Pressure Sensors
● Battery-Powered Instrumentation
Typical Application Circuit
Benefits and Features
● High Resolution for Industrial Applications that
Require a Wide Dynamic Range
• 133dB SNR at 50sps
• 124dB SNR at 1000sps
● Longer Battery Life for Portable Applications
• 2.2mA Operating Mode Current
1μA Sleep Current
● Single or Split Analog Supplies Provide Input Voltage
Range Flexibility
• 2.7V to 3.6V (Single Supply) or ±1.8V (Split Supply)
● Enables System Integration
• Low Noise, 6.2nV/Hz PGA with Gains of 1, 2, 4,
8, 16, 32, 64, 128
• 6-Channel, Fully Differential Input
● Enables On-Demand Device and System Gain and
Offset Calibration
• User-Programmable Offset and Gain Registers
● Robust Performance in a Small Package
• -40°C to +125°C Operating Temperature Range
• WLP Package, 3mm x 3mm (6 x 6 Ball Array)
2.7V TO 3.6V
REF
10nF 1µF 2.0V TO 3.6V
1nF
C0G
AIN0N
AIN5P
1nF
C0G
AIN0P
REFN REFP
AVDD
MAX11259
DVDD
RSTB
ADR0
SCL
ADR1
SDA
RDYB
AIN5N
GPO0 GPO1 GPOGND CAPP CAPN CAPREG AVSS
220nF
0603
X7R
1nF
C0G
RESISTIVE BRIDGE MEASUREMENT CIRCUIT, I2C CONFIGURATION
DGND
1µF
µC
19-7749; Rev 0; 9/15




MAX11259 pdf, 반도체, 판매, 대치품
MAX11259
24-Bit, 6-Channel, 16ksps, 6.2nV/√Hz PGA,
Delta-Sigma ADC with I2C Interface
Electrical Characteristics (continued)
(VAVDD = 3.6V, VAVSS = 0V, VDVDD = 2.0V to 3.6V, VREFP - VREFN = VAVDD, DATA RATE = 1ksps, PGA low-noise mode, single-cycle
conversion mode (SCYCLE = 1). TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)(Note 3)
PARAMETER
SYMBOL
Leakage Current (Off)
Ileak1
Ileak3
POWER-UP DELAYS (Note 6)
Power-Up Time
TPUPSLP
TPUPSBY
CONDITIONS
Current into the GPOGND bump
with one individual GPO_ bump
connected to 3V
Current into the GPOGND bump
with all GPO_ bumps connected
to 3V
SLEEP state (full power-down) to
LDO wake-up
VAVDD = 2.7V, VDVDD = 2.0V,
CAPREG = 220nF
STANDBY state (analog blocks
powered down, LDO on) to Active
MIN
TYP
0.4
13
23
4
MAX
UNITS
nA
160
50
µs
8
RDYB transition from ‘0’ to ‘1’ on
falling edge of RSTB, internal clock
mode (Note 6)
RSTB Fall to RDYB ‘1’
tR2 RDYB transition from ‘0’ to ‘1’ on
falling edge of RSTB, external clock
mode, clock frequency = fCLK (Note
6)
ANALOG INPUTS/REFERENCE INPUTS
Common-Mode Input
Voltage Range,
VCM = (VAIN_P +
VAIN_N)/2
CMIRNG
Direct (PGA bypassed)
PGA
Input Voltage Range
(AIN_P, AIN_N)
VIN(RNG)
Direct (PGA bypassed)
PGA
Differential Input
Voltage Range (AIN_P
– AIN_N)
DC Input Leakage
Differential Input
Conductance
Differential Input
Current
Common-Mode Input
Conductance
Common-Mode Input
Current
VIN(DIFF)
IIN_LEAK
GDIFF
Unipolar
Bipolar
SLEEP state enabled
Direct (PGA bypassed) (Note 6)
IDIFF
PGA enabled (Note 6)
GCM
Direct (PGA bypassed) (Note 6)
ICM PGA enabled (Note 6)
VAVSS
VAVSS
+ 0.4
VAVSS
VAVSS
+ 0.4
0
-VREF
±0.1
±11.6
±1.0
±1.0
±10
300
2/fCLK
VAVDD
VAVDD
- 1.3
VAVDD
VAVDD
- 1.3
VREF
+VREF
ns
s
V
V
V
nA
µA/V
nA
µA/V
nA
www.maximintegrated.com
Maxim Integrated 4

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MAX11259 전자부품, 판매, 대치품
MAX11259
24-Bit, 6-Channel, 16ksps, 6.2nV/√Hz PGA,
Delta-Sigma ADC with I2C Interface
Electrical Characteristics (continued)
(VAVDD = 3.6V, VAVSS = 0V, VDVDD = 2.0V to 3.6V, VREFP - VREFN = VAVDD, DATA RATE = 1ksps, PGA low-noise mode, single-cycle
conversion mode (SCYCLE = 1). TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)(Note 3)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
UVLO Threshold Low
to High
AVDD, DVDD supply undervoltage
lockout
0.75
VLH CAPREG supply undervoltage
lockout
0.6
1.2
1.0
1.7
1.4
V
UVLO Threshold High
to Low
AVDD, DVDD supply undervoltage
lockout
0.6
VHL CAPREG supply undervoltage
lockout
0.4
1.1
0.95
1.6
1.3
V
UVLO Hysteresis
UVLO Delay Low to
High or High to Low
UVLO Glitch
Suppression
VHYS
TDEL
TP
AVDD, DVDD supply undervoltage
lockout
CAPREG supply undervoltage
lockout
AVDD, DVDD supply undervoltage
lockout
CAPREG supply undervoltage
lockout
AVDD, DVDD supply undervoltage
lockout
CAPREG supply undervoltage
lockout
4
5
10
3.5
10
10
%
µs
ns
SDA
tf
SCL
S
tLOW
tHD;STA
tSU;DAT
tr tf
tHD;STA
tHD;DAT t HIGH
tSU;STA
Sr
Figure 1. I2C Timing Diagram
tSP t r tBUF
tSU;STO
P
S
www.maximintegrated.com
Maxim Integrated 7

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