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PDF W25Q40CL Data sheet ( Hoja de datos )
| Número de pieza | W25Q40CL | |
| Descripción | 2.5/3/3.3V 4 M-BIT SERIAL FLASH MEMORY | |
| Fabricantes | Winbond | |
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W25Q40CL
2.5/3/3.3V
4 M-BIT
SERIAL FLASH MEMORY WITH
4KB SECTORS, DUAL AND QUAD SPI
-1-
Publication Release Date: August 13, 2014
Revision D
1 page  
W25Q40CL
1. GENERAL DESCRIPTION
The W25Q40CL (4M-bit) Serial Flash memories provide a storage solution for systems with limited
space, pins and power. The 25Q series offers flexibility and performance well beyond ordinary Serial
Flash devices. They are ideal for code shadowing to RAM, executing code directly from Dual/Quad
SPI (XIP) and storing voice, text and data. The device operates on a single 2.3V to 3.6V power
supply with current consumption as low as 1mA active and 1µA for power-down. All devices are
offered in space-saving packages.
The W25Q40CL arrays are organized into 2048 programmable pages of 256-bytes each. Up to 256
bytes can be programmed at a time. The W25Q40CL have 128 erasable sectors, 16 erasable 32KB
blocks and 8 erasable 64KB blocks respectively. The small 4KB sectors allow for greater flexibility in
applications that require data and parameter storage. (See figure 2.)
The W25Q40CL support the standard Serial Peripheral Interface (SPI), and a high performance
Dual/Quad output as well as Dual/Quad I/O SPI: Serial Clock, Chip Select, Serial Data I/O0 (DI),
I/O1 (DO), I/O2 (/WP), and I/O3 (/HOLD). SPI clock frequencies of up to 104MHz are supported
allowing equivalent clock rates of 208MHz (104MHz x 2) for Dual I/O and 416MHz (104MHz x 4) for
Quad I/O when using the Fast Read Dual/Quad I/O instructions. These transfer rates can outperform
standard Asynchronous 8 and 16-bit Parallel Flash memories. The Continuous Read Mode allows
for efficient memory access with as few as 8-clocks of instruction-overhead to read a 24-bit address,
allowing true XIP (execute in place) operation.
A Hold pin, Write Protect pin and programmable write protect, with top, bottom or complement array
control, provide further control flexibility. Additionally, the device supports JEDEC standard
manufacturer and device identification with a 64-bit Unique Serial Number.
2. FEATURES
Family of SpiFlash Memories
– W25Q40CL: 4M-bit/512K-byte (524,288)
– 256-byte per programmable page
– Uniform 4KB Sectors, 32KB & 64KB Blocks
Software and Hardware Write Protection
– Write-Protect all or portion of memory
– Enable/Disable protection with /WP pin
– Top or bottom array protection
SPI with Single / Dual Outputs / I/O
Flexible Architecture with 4KB sectors
– Standard SPI: CLK, /CS, DI, DO, /WP, /Hold – Uniform Sector/Block Erase (4/32/64-kbytes)
– Dual SPI: CLK, /CS, IO0, IO1, /WP, /Hold
– Program one to 256 bytes < 1ms
– Quad SPI: CLK, /CS, IO0, IO1, IO2, IO3
– Erase/Program Suspend & Resume
Data Transfer up to 416M-bits / second
– Clock operation to 104MHz.
– More than 100,000 erase/write cycles
– More than 20-year data retention
– 208/416MHz equivalent Dual/Quad SPI
Low Power, Wide Temperature Range
– Auto-increment Read capability.
– Single 2.3 to 3.6V supply
Efficient “Continuous Read Mode”
– Low Instruction overhead
– 1mA active current, <1µA Power-down(typ.)
– -40°C to +85°C operating range
– Continuous Read
Space Efficient Packaging
– As few as 16 clocks to address memory
– 8-pin SOIC 150/208-mil
– Allows true XIP operation
– 8-pad USON 2x3mm
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Publication Release Date: August 13, 2014
Revision D
5 Page 
W25Q40CL
8. CONTROL AND STATUS REGISTERS
The Read Status Register-1 and Status Register-2 instructions can be used to provide status on the
availability of the Flash memory array, if the device is write enabled or disabled, the state of write
protection, Quad SPI setting, Security Register lock status and Erase/Program Suspend status. The
Write Status Register instruction can be used to configure the device write protection features, Quad SPI
setting and Security Register OTP lock. Write access to the Status Register is controlled by the state of
the non-volatile Status Register Protect bits (SRP0, SRP1), the Write Enable instruction, and during
Standard/Dual SPI operations, the /WP pin.
8.1 STATUS REGISTER
8.1.1 BUSY
BUSY is a read only bit in the status register (S0) that is set to a 1 state when the device is executing
a Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register
or Erase/Program Security Register instruction. During this time the device will ignore further
instructions except for the Read Status Register and Erase/Program Suspend instruction (see tW, tPP,
tSE, tBE, and tCE in AC Characteristics). When the program, erase or write status/security register
instruction has completed, the BUSY bit will be cleared to a 0 state indicating the device is ready for
further instructions.
8.1.2 Write Enable Latch (WEL)
Write Enable Latch (WEL) is a read only bit in the status register (S1) that is set to 1 after executing a
Write Enable Instruction. The WEL status bit is cleared to 0 when the device is write disabled. A write
disable state occurs upon power-up or after any of the following instructions finished: Write Disable,
Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register,
Erase Security Register and Program Security Register.
8.1.3 Block Protect Bits (BP2, BP1, BP0)
The Block Protect Bits (BP2, BP1, BP0) are non-volatile read/write bits in the status register (S4, S3,
and S2) that provide Write Protection control and status. Block Protect bits can be set using the Write
Status Register Instruction (see tW in AC characteristics). All, none or a portion of the memory array
can be protected from Program and Erase instructions (see Status Register Memory Protection table).
The factory default setting for the Block Protection Bits is 0, none of the array protected.
8.1.4 Top/Bottom Block Protect (TB)
The non-volatile Top/Bottom bit (TB) controls if the Block Protect Bits (BP2, BP1, BP0) protect from
the Top (TB=0) or the Bottom (TB=1) of the array as shown in the Status Register Memory Protection
table. The factory default setting is TB=0. The TB bit can be set with the Write Status Register
Instruction depending on the state of the SRP0, SRP1 and WEL bits.
8.1.5 Sector/Block Protect (SEC)
The non-volatile Sector/Block Protect bit (SEC) controls if the Block Protect Bits (BP2, BP1, BP0)
protect either 4KB Sectors (SEC=1) or 64KB Blocks (SEC=0) in the Top (TB=0) or the Bottom (TB=1)
of the array as shown in the Status Register Memory Protection table. The default setting is SEC=0.
- 11 -
Publication Release Date: August 13, 2014
Revision D
11 Page | ||
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